Single-loop c-band microwave synthesizer with a small frequency tuning step. Laboratory microwave synthesizer Microwave synthesizers articles

The creation of modern means of communication is impossible without the use of high-quality frequency synthesizers, which largely determine technical specifications radio systems. The article discusses high-performance wideband frequency synthesizers, and production company Maxim Integrated, which allow generating a reference signal in the range of 0.25...10 GHz. Low cost and excellent phase noise performance allow them to be used in a variety of applications - from personal radio communication systems to high-quality measuring instruments.

Humanity is increasingly using the radio frequency portion of the spectrum of electromagnetic waves, in particular the range of ultrashort waves with an oscillation frequency of 0.30...30 GHz. This vast range today is already quite densely filled with various radio communication systems with channels for transmitting digital data, entangled in network infrastructure on a local and global scale. The emergence of new systems and standards for wireless communications, satellite communications and navigation systems occurs in parallel with the improvement of semiconductor manufacturing technologies and contributes to rapid progress in the field of communication capabilities.

Satellite and cellular communications, wireless data transmission infrastructures: component requirements

One of the fundamental tasks in the design of any radio frequency equipment is to ensure high accuracy and stability of the carrier frequency, including amplitude and phase. This problem is solved today, as a rule, using specialized frequency synthesizers. A common option in this case is a phase-locked loop (PLL) synthesizer chip, which uses an external quartz reference frequency oscillator together with built-in dividers for the reference and generated output frequencies, a comparison circuit in the form of a frequency-phase discriminator (detector). The error signal is generated by a separate output stage (Charge Pump) and fed through an external (loop) filter to a voltage-controlled oscillator (VCO), which can be either built-in or external.

Programmable coefficients for Integer-N and Fractional-N modes, as well as the selection of the appropriate reference frequency, provide an expanded range of output frequencies and allow you to vary such parameters of the frequency synthesis process as the speed and step of frequency switching, and the level of phase noise.

Fractional-N synthesizers emerged largely as a solution to the problem of increasing frequency switching speed, reducing phase noise near the carrier frequency and reducing the level of spurious components in GSM and GPRS communication systems.

Synthesizers MAX2870, MAX2871, MAX2880. Features, advantages, recommendations for use

Maxim Integrated's range of semiconductor components today includes three ultra-wideband phase-locked loop (PLL) frequency synthesizer chips. All of them use a synthesis mechanism based on self-oscillators with PLL. The output frequency is set by the VCO and stabilized by a low-frequency reference oscillator.

Table 1. Maxim Integrated frequency synthesizers with PLL

Applications for Maxim Integrated frequency synthesizers include: telecommunications equipment, wireless equipment, measurement systems, clock generators in RF devices and analog-to-digital converters.

Synthesizer MAX2870

The ultra-wideband MAX2870 phase-locked loop with integrated VCO is capable of both integer and fractional frequency synthesis. Combined with external reference generator and external filter MAX2870 allows you to create highly efficient, low-noise circuits in the range of 23.5 MHz...6 GHz.

Generating frequencies in an extended range is provided using several integrated VCOs and output dividers with coefficients of 1...28. There are two software-settable, independent differential outputs that can provide output power of -4...5 dBm. Both outputs can be disabled by software or hardware.

The MAX2870 is controlled via 3-wire serial interface. The chip is produced in a miniature 32-pin QFN package. It is capable of operating in the temperature range -40…85°C.

The functional diagram of the MAX2870 is shown in Figure 1. The main elements of the device are a control interface and registers block (SPI AND REGISTERS), several counters and dividers, several VCOs (VCOs) and multiplexers. Four output signals (RFOUTx_x) are taken through switches from two differential amplifiers. To adjust the synthesized frequency there is a CHARGE PUMP block and a TUNE input.

To control the MAX 2870, there are five 32-bit registers for writing data, and one register for reading. The most significant 29 bits (MSB) are for data, and the least significant 3 bits (LSB) define the register address. The data in the registers is loaded via the SPI serial interface, the 29 MSB bits are transferred first. Programmable registers have addresses 0x05, 0x04, 0x03, 0x02, 0x01 and 0x00.

Figure 2 shows a timing diagram of the recording process via SPI. After power is applied, all registers must be programmed twice with a minimum pause of 20 ms between entries. The first entry makes sure that the device is turned on, and the second entry starts the VCO.

The MAX2870 can be put into low power mode by setting SHDN = 1 (Register 2, bit 5) or by setting the CE pin low. After exiting power-down mode, it takes at least 20 ms for the external capacitors to charge before programming the VCO frequency.

The input reference frequency goes through the RF_IN input to the inverting buffer and then through the optional x2 multiplier and muxer to the R COUNTER divider, then through the optional divider and multiplexer it reaches phase detector and output multiplexer.

When the x2 multiplier is enabled (DBR = 1), the maximum reference frequency is limited to 100 MHz. When the multiplier is disabled, the reference input frequency is limited to 200 MHz. The minimum reference frequency is 10 MHz. The minimum division factor R is 1, and the maximum is 1023.

The phase detector frequency is determined as follows:

where fREF is the frequency of the input reference signal. DBR (Register 2, bit 25) sets the fREF input frequency doubling mode. RDIV2 (Register 2, bit 24) sets fREF to divide mode by 2. R (Register 2, bits 23:14) is the value of a 10-bit programmable counter (1 to 1023). The maximum fPFD value is 50 MHz for Frac-N mode and 105 MHz for Int-N mode. The R divisor can be set to zero when RST (Register 2, bit 3) is 1.

The VCO frequency (fVCO), N, F and M values ​​can be determined based on the required output frequency of channel A (fRFOUTA) as follows. The DIVA divider value can be set based on the fRFOUTA values ​​from the DIVA value table (register 4, bits 22…20).

If FB bit = 1, (DIVA is excluded from feedback PLL):

If FB bit = 0, (DIVA in PLL feedback) and DIVA ≤ 16:

If FB bit = 0, (DIVA in PLL feedback) and DIVA > 16:

Here N is the value of the 16-bit counter N (16...65535), programmable through register 0, bits 30...15. M – fractional module value (2…4095), programmed via bits 14…3 of register 1. F – fractional division value, programmed via bits 14…3 of register 0.

In fractional (Frac-N) mode, the minimum value of N is 19 and the maximum is 4091. The N counter is reset when RST is 1 (Register 2, bit 3). DIVA – RF output division setting (0…7), programmable via bits 22…20 of register 4. The division coefficient is set as 2DIVA.

The output frequency of channel B (fRFOUTB) is determined as follows:

If BDIV = 0 (register 4, bit 9),

If BDIV = 1,

Int-N/Frac-N modes

Integer division mode (Int-N) is selected by setting the INT bit = 1 (register 0, bit 31). When operating in this mode, it is also necessary to set the LDF bit (Register 2, bit 8) to enable the synchronization timing (frequency lock) function in Integer-N mode.

Fractional division mode (Frac-N) is selected by setting the INT bit = 0 (register 0, bit 31). Additionally, set the LDF bit = 0 (register 2, bit 8) for the Frac-N synchronization mode.

If the device remains in Frac-N mode with the fractional division set to F = 0, unwanted transient noise may occur. To avoid this, you can enable autoswitching to Integer-N mode when F = 0 by setting bit F01 = 1 (Register 5, bit 24).

Phase detector and control voltage generation (Charge Pump)

The charge current generated by the Charge Pump for the external capacitor is determined by the value of the resistor connected between the RSET pin and the common wire, and the value of the CP bits (register 2, bits 12 ... 9) as follows:

To improve stability in Frac-N mode, set the linearity bit CPL = 1 (Register 1, bits 30, 29). For Int-N mode, set CPL = 0. To reduce noise in Int-N mode, set CPOC bit = 1 (Register 1, bit 31) to prevent current leakage into the loop filter. For Frac-N mode, set CPOC = 0.

The CP_OUT output can be driven into a high impedance state when TRI = 1 (register 2, bit 4). When TRI = 0 this output is normal condition. The polarity of the phase detector signal can be reversed for an active inverting loop filter. For a non-inverting filter, set PDP = 1 (register 2, bit 6). For the inverting filter, set PDP = 0.

MUX_OUT and LD (Lock Detect) outputs

MUX_OUT is a multi-purpose test output for monitoring various internal operations of the MAX2870. MUX_OUT can also be configured for serial output. The MUX bits (register 2, bits 28…26) allow you to select the type of signal on MUX_OUT.

The Lock detect signal can be monitored via the LD output by setting the LD bits (register 5, bits 23…22). For digital timing detection, set LD = 01. Digital timing detection depends on the synthesis mode. In Frac-N mode, set LDF = 0, and in Int-N mode, set LDF = 1. You can also set the accuracy of digital timing detection according to the tables.

Analog timing detection can be used with a setting of LD = 10. In this mode, LD uses an open collector output that requires an external pull-up resistor.

The accuracy of the timing detection output depends on many factors. The output value may not be reliable during the VCO autoselection process. Once this process is complete, the output is still unreliable until the tuning voltage is established. The VTUNE settling time depends on the loop filter bandwidth and can be calculated using the EE-Sim Simulation software tool.

Fast-Lock Mode

The MAX2870 chip has a fast-lock mode. In this mode, CP = 0000 (register 2, bits 12...9), and a divider of two resistors with a ratio of nominal values ​​of 1/3 is connected to the SW output. A larger resistor is connected between the output and the common power pin, and a smaller resistor is connected between the SW pin and the filter capacitor. When CDM = 01 (Register 3, bits 16...15), fast clocking begins to operate after the VCO autoselect process has completed.

During the process of accelerated synchronization, the Charge Pump charging current increases to the value determined by CP = 1111, and the ratio between the resistors shunting the loop filter becomes equal to 1/4 due to the transfer of the SW output to a high-impedance state. Fast-Lock is deactivated after a user-specified timeout. This timeout is equal to:

Here M is the adjustable coefficient, and CDIV is the divider setting. The designer must determine the CDIV settings based on the feedback filter time constant.

Outputs RFOUTA± and RFOUTB±

The chip has two open-collector differential RF outputs that require external 50-ohm resistors to be connected to each output.

Each output can be independently enabled or disabled by setting the RFA_EN (Register 4, Bit 5) and RFB_EN (Register 4, Bit 8) bits. Both outputs can also be controlled via the RFOUT_EN pin.

The output power of each output is configurable separately via APWR (register 4, bits 4, 3) for RFOUTA and BPWR (register 4, bits 7...6) for RFOUTB. It is possible to adjust the power of the differential output in the range of -4...5 dBm, in steps of 3 dB when operating into a 50 Ohm load. It is also possible to adjust in the same range for an unbalanced output with power supplied through an RF choke. For optimal output level, different load elements are required across the entire frequency range. If a single-ended output is used, the unused output must be connected to an appropriate load (Table 2).

Table 2. MAX2870 pin assignments

VCO (VCO)

The chip contains four 16-band separate VCO blocks, which provide continuous coverage of the frequency range 3...6 GHz. To operate the VCO, the output of the external feedback filter must be connected to the TUNE input, which controls the operation of the VCO. The control voltage is supplied through the filter from the CP_OUT output (Figure 3).

The MAX2870 includes a 3-bit ADC to read the VCO voltage setting range. ADC values ​​can be read from register 6, bits 22...20.

Please note that a lock detect signal may appear if the VCO tuning voltage is outside the appropriate range.

Auto VCO selection

The VCO autoselection (VAS) mode is enabled when the VAS_SHDN bit is set to 0 (register 3, bit 25). If VAS_SHDN = 1, then the VCO can be set manually via the VCO bits (Register 3, bits 31...26). The RETUNE bit (Register 3, bit 24) is used to enable/disable the VCO autoselect function. If RETUNE = 1 and the ADC detects that the VTU tuning voltage is between 000 and 111, the VAS function initiates auto tuning. If RETUNE = 0, this feature is disabled.

The fBS clock frequency should be 50 kHz. It is set by the BS bits (register 4, 19...12). The required BS value is calculated using the formula:

Where fPFD is the frequency of the phase detector. The BS value should be rounded to the nearest whole number. If the calculated BS value is greater than 1023, then BS = 1023. If fPFD is below 50 kHz, then BS = 1. The time required to select the VCO correctly is 10/fBS.

Phase adjustment

Once the target frequency is established, the phase of the RF output signal can be discretely changed in steps of P/M × 360°. The phase cannot be determined absolutely, but it can be changed relative to the current value.

To change the phase, do the following:

• set the desired output frequency;
• set the phase increment relative to the current value P = M × (phase change)/360°;
• enable phase change by setting CDM = 10;
• reset the CDM to 0.

Synthesizer MAX2871

Ultra Wideband MAX2871 with a PLL and an integrated VCO, it is capable of operating in both integer and fractional frequency synthesis modes. When combined with an external reference generator and loop filter, the MAX2871 is used in high-performance, low-noise applications operating in the 0.235 to 6 GHz range. The MAX2871 also includes four integrated VCOs and two differential outputs with software adjustable power level -4...5 dBm. Both outputs can be disabled by software or hardware.

The chip is produced in a miniature 32-pin QFN package. It is completely interchangeable with the MAX2870. The MAX2871 operates in a temperature range of -40...85°C. The functional design of the MAX2871 is the same as the MAX2870 (Figure 1). However, the MAX2871 offers enhanced functionality, lower noise levels, and an integrated temperature sensor with a 7-bit ADC that is accurate to ±3°C.

VCO voltage setting

Unlike the 3-bit ADC in the MAX2870, the MAX2871 uses a 7-bit ADC to read the VCO voltage, the values ​​of which can be read through register 6, bits 22...16. To digitize the voltage you need to do the following:

• set CDIV bits (register 3, bits 14...3) = fPFD/100 kHz to select the clock frequency for the ADC;
• set ADCM bits (register 5, bits 5...3) = 100 to allow the ADC to read the voltage at the TUNE pin;
• set ADCS (register 5, bit 6) = 1 to start the ADC conversion process;
• wait 100 µs for the process to complete;
• read the value of register 6. The ADC value is located in bits 22…16;
• reset bits ADCM = 0 and ADCS = 0.

The voltage at the TUNE pin can be calculated as follows:

Auto VCO selection

For the MAX2871, additional options are available when selecting the VCO to use. The VAS_TEMP bit (Register 3, bit 24) can be used to select the optimal VCO according to the ambient temperature to ensure timing stability in the range -40 to 85°C. During the VCO selection process, bits RFA_EN (Register 4, bit 5) and RFB_EN (Register 4, bit 8) must be set to 0, and bits 30, 29 of register 5 must be set to 11. Setting VAS_TEMP = 1 will increase the time required to set the desired frequency, approximately from 10/fBS to 100 ms.

temperature sensor

To calculate the temperature of the crystal, the MAX2871 has a built-in temperature sensor with a 7-bit ADC, the state of which is read through register 6. In this case, you need to go through almost the same sequence of steps as when setting the VCO voltage. The exception is the second point:

• Set the ADCM bits (Register 5, bits 5...3) = 001 to enable the ADC to read the temperature.

The approximate temperature can be obtained as follows:

This formula is most accurate with the VCO enabled and full output power at RFOUTA.

Outputs RFOUTA± and RFOUTB±

Where CDIV (register 3, bits 14...3) is the value of the 12-bit divider, M (register 1, bits 14...3) is the variable coefficient for the fractional converter N, and fPFD is the frequency of the phase detector.

PLL tracking failure

To ensure stable synchronization of a given frequency, in addition to the Fast-Lock method, the MAX2871 has Cycle Slip reduction, which is enabled by setting the CSM bit (register 3, bit 18) to 1. In this mode, the minimum value of the control charge pump current at the output of the CP block is ensured.

Compared to the MAX2870, the MAX2871 also has advanced capabilities for adjusting the phase of the output frequency signal.

Synthesizer MAX2880

The final model in the Maxim Integrated line of synthesizers is MAX2880 with a PLL system, using an external VCO and capable of operating over an even wider frequency range. Together with an external reference oscillator, VCO, and filter, the MAX2880 produces low-noise RF output frequencies in the range of 0.25 to 12.4 GHz. The MAX2880 uses a built-in temperature sensor. Available in two versions: a 20-pin TQFN package and a 16-pin TSSOP package, which are capable of operating in an extended operating temperature range of -40...85°C.

The functional diagram of the MAX2880 is shown in Figure 4. The principle of its operation and a number of components are similar to those used in the MAX2870 and MAX2871. The MAX2880 includes a high-precision, low-noise phase detector (PFD) and precision loop filter capacitor Charge Pump, a 10-bit programmable reference divider, a 16-bit Integer N divider, and a 12-bit variable ratio fractional converter.

The 3-wire control interface with five registers for writing and one for reading, which has a channel for dividing the reference frequency from the REF input, is similar to the previously discussed one. But at the same time, the MAX2880 does not have a built-in VCO unit, but uses an external VCO controlled from the CP output. You can put the MAX2880 into low power mode by setting SHDN = 1 (register 3, bit 5) or, as in other MAX synthesizers, by setting the CE pin low.

The MAX2880 phase detector frequency is determined by the following formula:

Here fREF is the input reference frequency. DBR (Register 2, bit 20) sets the input frequency doubling mode fREF. RDIV2 (register 2, bit 21) sets the fREF division mode by 2. R (register 2, bits 19...15) – value of the 5-bit programmable reference divider (1...31). The maximum fPFD is 105 MHz for Fractional-N and 140 MHz for Integer-N. The R divider is cleared when RST (Register 3, bit 3) = 1.

The frequency of the external VCO is determined by the formula:

Where N is the value of the 16-bit N divisor (16...65535), programmable through bits 30...27 (MSB) of register 1 and bits 26...15 of register 0 (LSB). M – fractional coefficient value (2…4095), programmable via bits 14…3 of register 2. F – fractional division value, programmable via bits 14…3 of register 0. In Fractional-N mode, the minimum value of N is 19, and the maximum is 4091 The N divider is cleared when RST = 1 (register 3, bit 3). PRE – control of the input prescaler, where 0 means division by 1, and 1 means division by 2 (register 1, bit 25). If the input frequency is higher than 6.2 GHz, then PRE = 1.

RF inputs

The RF differential inputs (Table 3) are connected to high-impedance input buffers that drive the demultiplexer to select one of two frequency ranges, 0.25...6.2 GHz or 6.2...12.4 GHz. For operation in the upper range, a predivisor by 2 is used, selected by setting the PRE bit = 1. When operating in a single-channel version, the unused RF input is connected to the common pin through a 100 pF capacitor.

A possible connection diagram for the MAX2880 is shown in Figure 5.

Table 3. MAX2880 pin assignments

Development Tools: Demo Boards and Software

Special hardware and software tools from Maxim Integrated can significantly simplify the development process and reduce the duration of implementation of new solutions.

MAX2870/MAX2871 Evaluation Kit Boards

Demo boards MAX2870/MAX2871(Figure 6) make it easy to test and evaluate the MAX2870 and MAX2871 synthesizers. Each board is equipped with standard SMA connectors for connecting input signal sources, 50 Ohm loads, signal or spectrum analyzers. There is a USB connector for connecting to a computer with pre-installed special software.

The sequence of actions when working with evaluation boards is as follows.

• download software from the website www.maximintegrated.com/evkitsoftware;
• unpack and install this software (Figure 7);
• after running the MAX287x.exe file, you need to select the type of chip (MAX2870 or MAX2871) and click the “Continue” button. A working graphical interface will appear on the screen;
• check the USB cable connection using the green rectangle in the lower right corner of the working screen;
• make sure the board's TCXO (U2) frequency matches REF.FREQ software. If not, enter the required value in MHz (default 50) and press “Enter”;
• click the “Defaults” and then “Send All” buttons located at the top of the working screen;
• enter the required output frequency value in MHz in the RF_OUTA or RF_OUTB window and press “Enter”;
• Make sure the PLL Lock indicator in the lower left corner is green.

Use a signal analyzer to evaluate the performance of the MAX2870 or MAX2871. The default is an external 50 MHz reference. But other values ​​can be used after changing the values ​​in the programmable registers accordingly.

Output level

To equalize the load of unused outputs, 3 dB attenuators are used with them. Thus, the measured power at the outputs of the evaluation board (SMA connectors) becomes 3 dB lower than the actual level. To measure the true value of the output level, remove the attenuators and connect a 50 ohm load to all active unused outputs.

Export/import register settings

To export register settings from the MAX2870/MAX2871, follow these steps:

• select “Reg → Clip” in the lower left corner of the working screen with the mouse, after which the register values ​​will be saved to the clipboard;
• paste the contents of the clipboard into any test editor.
• To import settings for the MAX2870/MAX2871 registers, follow these steps:
• copy register settings (comma separated) from a text editor to the clipboard;
• select “Clip → Reg” in the lower left corner of the working screen;
• Click the “Send All” button in the upper right corner of the home screen.

MAX2880 Evaluation Kit Board

The MAX2880 evaluation board includes a full-bandwidth PLL synthesizer, an external 5840-6040 MHz VCO, a 50 MHz temperature-compensated crystal oscillator (TCXO), a passive feedback filter, and low-dropout regulators.

The software runs on computers running Windows starting from version XP.

In addition, the MAX2880 Evaluation Kit requires a Maxim INTF-3000-to-USB interface board, a 20-wire ribbon cable between the interface and evaluation boards. To connect the evaluation board to a computer, you need a USB type A to type B cable. The evaluation board also requires an external power supply of 6 V/150 mA.

The connection diagram is shown in Figure 8, and the boards themselves are shown in Figure 9.

The software for operation is downloaded from the website www.maximintegrated.com. The installation and operation process is the same as described for the MAX2870/MAX2871 Evaluation Kit. The working screen of the program is shown in Figure 10.

Conclusion

Maxim Integrated's MAX2870, MAX2871, and MAX2880 frequency synthesizers provide extended RF performance and can be used in high-precision microwave sources in a variety of telecommunications, navigation, and measurement applications.

The demo boards and specialized software offered by the company allow us to speed up the process of developing, configuring and implementing samples of new equipment.

Literature

1. https://datasheets.maximintegrated.com/en/ds/MAX2870.pdf.
2. https://datasheets.maximintegrated.com/en/ds/MAX2871.pdf.
3. https://datasheets.maximintegrated.com/en/ds/MAX2880.pdf.
4. https://datasheets.maximintegrated.com/en/ds/MAX2870EVKIT.pdf.
5. https://datasheets.maximintegrated.com/en/ds/MAX2880EVKIT.pdf.

and - low-noise differential op-amps

MAX44205 And MAX44206 production company Maxim Integrated are low-noise, fully differential op-amps designed to drive precision, high-speed 16/18/20-bit A/D converters, such as .
A unique combination of characteristics, a wide range of supply voltages (2.7 ... 13.2 V), low power consumption and wide bandwidth allow them to be used in high-performance, low-power data acquisition systems.
Both amplifiers, through the VCOM pin, allow you to control the common-mode output voltage, which in some cases significantly simplifies the circuit design of the measuring channel and normalizes the DC component of the output signal according to the requirements of the ADC.
The MAX44205 features an optional output voltage limiting feature that allows it to be limited to within the ADC's full scale when the amplifier supply voltage is higher than the maximum permissible input voltage of the converter.
In low power mode, the amplifiers consume only 6.8 µA of current, extending battery life in stand-alone measurement systems or reducing overall system power consumption between measurements.
The amplifiers are available in small, solder-friendly 12-lead µMAX® and 10-lead TDFN packages. Operating temperature range -40…125°C.
A demo board has been developed to evaluate amplifier parameters MAX44205EVKIT#. Also the MAX44205 is used as an ADC driver on the demo board MAX11905DIFEVKIT#.
Recommended amplifier applications:

• active filters;
• high-speed process control systems;
• Medical equipment;
• conversion of common-mode signals into differential ones;
• differential signal processing.

Owners of patent RU 2580068:

The invention relates to radio engineering and can be used in transmitting and receiving devices in the microwave frequency range. The technical result is to increase stable operation when tuning the frequency of the input microwave signal. The microwave frequency synthesizer contains a microwave voltage-controlled oscillator (VCO), a directional coupler, a microwave mixer, a source of an input microwave signal, a first frequency divider with a variable division coefficient, a frequency-phase detector, a second frequency divider with a variable division coefficient, a reference signal source, and a filter. low pass, phase comparator, standby multivibrator, two diodes and an operational amplifier. 4 ill.

The invention relates to radio engineering, namely to wide-range microwave frequency synthesizers with preliminary, initial, frequency setting of a microwave voltage-controlled oscillator (VCO), included in a wide-range phase-locked loop (PLL) system of a microwave frequency synthesizer and can be used in transceiver devices of the microwave frequency range .

Active frequency synthesis systems are known, in which the oscillations of the synthesized frequencies are filtered using an active filter in the form of a phase-locked loop. In this case, the signal frequency is converted, for example, by division into the low-frequency range, where it is compared with the frequency of the reference oscillator and the auto-tuning voltage of a voltage-controlled microwave oscillator (VCO) is generated. Active synthesis systems provide higher suppression of spurious spectral components and phase noise of the carrier wave. However, in this circuit, due to the high frequency division ratio of the VCO, it is impossible to achieve a low noise level in the synthesizer output signal.

A microwave frequency synthesizer is known that implements the principle of active synthesis with a PLL loop, which was chosen as a prototype of the proposed invention. The microwave frequency synthesizer contains a microwave VCO, the output of which is connected through a directional coupler to the output of the microwave frequency synthesizer and to the first input of the microwave mixer, the second input of which is connected to the output of the source of the input microwave signal with frequency f microwave input, the output of the microwave mixer is connected to the input of the first frequency divider (DF) with a variable division coefficient n, the output of which is connected to the first input of the frequency-phase detector (FPD), the second input of the frequency-phase detector is connected to the output of the second frequency divider with a variable division coefficient m, the input of which is connected to the source of the reference frequency signal f OP, and the output of the frequency-phase detector is connected through a low-pass filter (LPF) to the input of the microwave VCO. In this case, the directional coupler, mixer, first frequency divider, PFD and low-pass filter form a PLL loop.

The known microwave frequency synthesizer makes it possible to achieve a low level of phase noise in the output signal of a microwave frequency synthesizer with a frequency f MF by reducing the division coefficient of the first frequency divider when used as an input microwave signal with a frequency f input microwave signal with a low level of phase noise. In addition, reducing the division ratio of the first frequency divider allows you to increase the gain of the PLL loop. Since in such a circuit the frequency of the input microwave signal f in microwave is selected from the condition f in microwave >f MF, then in order to maintain a constant value of the gain of the PLL loop of the microwave frequency synthesizer, it is necessary to compensate for the change in the division coefficient of the first frequency divider by changing the frequency tuning slope of the microwave VCO to maintain PLL loop control bands.

However, if the frequency drifts f VCO microwave VCO are more than 2 f IF (where intermediate frequency f IF = f input microwave - f VCO), then phase synchronization failures will occur in this microwave frequency synthesizer, which will lead to loss of functionality of the synthesizer.

In addition, the known microwave frequency synthesizer works only if an input microwave signal with a fixed frequency f microwave input is supplied to the second input of the microwave mixer. When an input microwave signal with a variable (tunable) frequency f in microwave is supplied to this input of the microwave mixer in a band greater than or equal to 2 f IF, phase synchronization violations may also occur in the microwave frequency synthesizer.

The technical objective of the present invention is to create a wide-range microwave frequency synthesizer with a low level of phase noise and a short tuning time for the frequency of the output signal of the synthesizer f MF, ensuring the absence of phase synchronization violations when changing (tuning) the frequency of the input microwave signal f input microwave in a band equal to or greater than double the frequency of the intermediate frequency signal f IF, where f IF = f input microwave -f VCO, as well as ensuring the preservation of phase synchronization when the frequency f VCO of the microwave VCO signal moves by more than 2 f IF.

The technical result is to prevent violations of phase synchronization caused by transient processes in the PLL loop, and to ensure stable operation of the microwave frequency synthesizer during operation, including when tuning the frequency f input of the microwave input signal

Essence technical solution lies in the fact that the proposed microwave frequency synthesizer contains a voltage-controlled microwave oscillator (VCO), the output of which is connected to the input of a directional coupler, the first output of which is the output of the microwave frequency synthesizer, and the second output of the directional coupler is connected to the first input of the microwave mixer, the second input The microwave mixer is connected to the output of the source of the input microwave signal, the output of the microwave mixer is connected to the input of the first frequency divider with a variable division coefficient, the output of which is connected to the first input of the frequency-phase detector, the second input of the frequency-phase detector is connected to the output of the second frequency divider with a variable division coefficient division, the input of which is connected to the output of the reference signal source, and a low-pass filter is connected between the frequency-phase detector and the microwave VCO. The microwave frequency synthesizer additionally contains a phase comparator, a standby multivibrator, two diodes and an operational amplifier. In this case, the first and second outputs of the frequency-phase detector are connected, respectively, to the first and second inputs of the operational amplifier, the output of which is connected to the input of the microwave VCO, and a low-pass filter is connected between the first input of the operational amplifier and its output, the first input of the phase comparator is connected to the output of the first frequency divider with a variable division coefficient and the first input of the frequency-phase detector, the second input of the phase comparator is connected to the output of the second frequency divider with a variable division coefficient and to the second input of the frequency-phase detector, the output of the phase comparator is connected to the input of the waiting multivibrator, the first output of the waiting multivibrator connected through the first diode to the first output of the frequency-phase detector and to the first input of the operational amplifier, the second output of the standby multivibrator is connected through the second diode to the second output of the frequency-phase detector and to the second input of the operational amplifier. Moreover, the first and second diodes are connected opposite each other, while the microwave VCO, directional coupler, microwave mixer, first frequency divider, frequency-phase detector, operational amplifier and low-pass filter form a phase-locked loop (PLL) provided: T M - τ m >τ PLL, where T M is the oscillation period of the waiting multivibrator, τ PLL is the time to establish synchronization in the phase-locked loop.

The inclusion of a phase comparator and a standby multivibrator with two back-to-back diodes at the output into the circuit of the microwave frequency synthesizer allows for preliminary setting of the frequency f of the VCO signal of the microwave VCO in the event of a violation of phase synchronization in the PLL loop, which occurs when switching the frequency f of the input microwave signal or when leaving frequency f VCO of the microwave VCO signal, for example, when turning on the microwave synthesizer, which ensures rapid restoration of phase synchronization and increases the stability of the microwave frequency synthesizer. In this case, after the PLL loop is restored, the standby multivibrator is turned off and does not affect the further operation of the PLL loop.

An operational amplifier with a low-pass filter in the feedback circuit forms the control bandwidth of the PLL loop.

The time between the end of the first pulse and the beginning of the next pulse of the waiting multivibrator, determined by the RC circuit of this multivibrator, must be greater than the time to establish synchronization in the PLL loop, that is, the condition must be met:

T M -τ m >τ PLL.

The invention is illustrated by drawings.

In fig. Figure 1 shows a block diagram of the proposed microwave frequency synthesizer, where

1 - microwave generator (VCO) with frequency f VCO (control voltage U UPR);

3 - microwave mixer;

4 - source of input microwave signal with frequency f microwave input;

5 - first frequency divider with variable division ratio n;

6 - frequency-phase detector ( output voltage U CFD);

7 - second frequency divider with variable division ratio m;

8 - source of reference signal with frequency f OP;

9 - operational amplifier;

10 - low pass filter;

11 - phase comparator (output voltage U FC);

12 - standby multivibrator (direct output voltage U m1 and inverse

13 - first diode;

14 - second diode;

f IF =f microwave input -f VCO - intermediate frequency signal;

f MF - output signal of the microwave frequency synthesizer.

In fig. Figure 2 shows the timing diagrams of the input U FC and output voltages U m1 and U m2 of the waiting multivibrator, which is part of the proposed microwave frequency synthesizer, where

T M - oscillation period of the waiting multivibrator 12;

τ m - pulse duration of the waiting multivibrator 12;

τ PLL is the time to establish synchronization in the phase-locked loop.

In fig. Figure 3 shows the tuning bandwidth of the output microwave signal with frequency f MF =f VCO relative to the fixed frequency f input microwave signal of the proposed microwave frequency synthesizer.

In fig. Figure 4 shows the tuning bandwidth of the output microwave signal with frequency f MF =f VCO relative to the tunable frequency f input microwave input signal of the proposed microwave frequency synthesizer.

The proposed microwave frequency synthesizer, the block diagram of which is shown in Fig. 1, contains a microwave voltage-controlled generator (VCO) 1, the output of which is connected to the input of a directional coupler 2, one output of which is the output of a microwave frequency synthesizer, and the other output of the directional coupler 2 is connected to the first input of a microwave mixer 3, the second input of which is connected to the output source of input microwave signal 4 with frequency f microwave input. The output of the microwave mixer 3 is connected to the input of the first frequency divider 5 with a variable division coefficient n, the output of which is connected to the first input of the frequency-phase detector 6. The second input of the frequency-phase detector 6 is connected to the output of the second frequency divider 7 with a variable division coefficient m, input which is connected to the output of the reference signal source 8 with frequency f OP. Two outputs of the frequency-phase detector 6 are connected to two inputs of the operational amplifier 9, the output of which is connected to the input of the microwave VCO generator 1, while a low-pass filter 10 is connected between the first input of the operational amplifier 9 and its output. The first input of a phase comparator additionally introduced into the circuit 11 is connected to the output of the first frequency divider 5 and the first input of the frequency-phase detector 6, the second input of the phase comparator 11 is connected to the output of the second frequency divider 7 and the second input of the frequency-phase detector 6. The output of the phase comparator 11 is connected to the input of the waiting multivibrator 12, direct the output of which through the first diode 13 is connected to the first output of the frequency-phase detector and the first input of the operational amplifier 9, the inverse output of the standby multivibrator 12 through the second diode 14 is connected to the second output of the frequency-phase detector 6 and to the second input of the operational amplifier 9, the first and the second diodes are connected opposite each other. In this circuit, microwave VCO 1, directional coupler 2, microwave mixer 3, first frequency divider 5, frequency-phase detector 6, second frequency divider 7, operational amplifier 9 and low-pass filter 10 form a PLL loop.

The proposed microwave frequency synthesizer works as follows. The output signal of microwave VCO 1 with frequency f VCO through coupler 2 and the output microwave signal of the input microwave signal source 4 with frequency f input microwave is supplied to microwave mixer 3, at the output of which a signal of intermediate frequency f IF is selected, which is fed to the input of the first frequency divider 5 and after dividing by a factor n, the signal from the output of the first frequency divider 5 is supplied to the first input of the frequency-phase detector 6. The reference frequency signal f OP from the output of the reference signal source 8 is supplied to the input of the second frequency divider 7, where the frequency is divided by a factor m. The signal from the output of the second frequency divider 7 is supplied to the second input of the frequency-phase detector (FPD) 6, in which it is compared with the signal received from the output of the first frequency divider 5, and a control voltage U FPD is generated at the two outputs of the frequency-phase detector 6, the magnitude and sign of which are proportional to the difference in frequencies and phases of the compared signals. This control voltage U PFD through the operational amplifier 9 and the low-pass filter 10, included in the feedback circuit of the operational amplifier 9, is supplied to the control input of the microwave VCO 1 as the control voltage U Ctrl., performing a continuous adjustment of the frequency of the microwave VCO 1, affecting the phase mode synchronization in the PLL loop.

The conditions for performing frequency-phase synchronization in the PLL loop are the equality of the frequencies and phases of the signals supplied to the inputs of the frequency-phase detector, that is, f OP /m=f IF /n, φ OP =φ IF,

where f IF = f input microwave -f VCO,

m is the coefficient of division of the frequency of the reference signal with frequency f OP;

n is the frequency division factor of the intermediate frequency signal f IF;

φ OP - phase of the reference signal with frequency f OP;

φ IF - phase of the intermediate frequency signal f IF.

When the frequency of the input microwave signal f in microwave is adjusted in a band equal to or greater than twice the frequency of the intermediate frequency signal f IF, where f IF = f in microwave -f VCO, as well as when the frequency of the microwave signal f VCO f VCO moves by more than 2 f IF, input microwave signal f input microwave in the proposed invention passes through the PLL loop of the microwave frequency synthesizer, that is, through the phase comparator 11, the waiting multivibrator 12, as well as back-to-back diodes 13, 14.

If there is phase synchronization in the PLL loop, a control signal is received from the output of the phase comparator 11 to the waiting multivibrator 12, which turns off the waiting multivibrator 12, that is, the output voltage of the phase comparator 11 U FC (for example, the level of transistor-transistor logic TTL) in the form of a logical unit. At this time, the waiting multivibrator 12 does not produce pulsed output signals with voltages U M1, U M2 at the direct and inverse outputs, respectively, and does not affect the operation of the PLL loop. At the direct and inverse outputs of the waiting multivibrator 12, constant voltages U M1 and U M2 are set in antiphase, corresponding to logical zero and logical one). The timing diagrams of the input U FC and output voltages U M1 and U M2 of the waiting multivibrator 12 are shown in Fig. 2

If the frequency and phase synchronization in the PLL loop is disturbed, the U FC signal in the form of a logical zero from the output of the phase comparator 11 triggers the standby multivibrator 12, which at the direct and inverse outputs produces output pulse signals with voltages U M1 (corresponding to a logical unit) and U M2 (corresponding logical zero), arriving through diodes 13, 14, respectively, to the first and second inputs of the operational amplifier 9. During the action of the pulse of the waiting multivibrator 12, that is, during the duration τ m of the pulse of the waiting multivibrator 12, depending on the phasing of the inputs of the PFD 6, at the output operational amplifier 9 sets the maximum or minimum value of the control voltage for the frequency of the signal of the microwave VCO 1. In this case, the conditions for frequency-phase synchronization are violated (f OP /m=f IF /n, φ OP =φ IF) and the frequency-phase detector 6 generates a control voltage U PFD, which ensures the restoration of synchronization (that is, the start of the synchronization process) in the PLL loop. When frequency-phase synchronization is restored in the PLL loop, the phase comparator 11 turns off the standby multivibrator 12 (at its outputs, constant voltages corresponding to logical zero and logical one are again set in antiphase). In the event of a repeated violation of the frequency-phase synchronization in the PLL loop or in the event of a malfunction of the PLL loop, the phase comparator 11 again starts the waiting multivibrator 12 and the entire process of restoring synchronization is repeated.

In some cases, for the operation of the PLL loop, excluding the violation of frequency-phase synchronization in it, it is necessary that the transient process of tuning the frequency of the microwave VCO in the PLL loop begins from the lower (f VCO min) or upper (f VCO max) edge of the operating range of the microwave VCO to the frequency capture point at which f VCO = f MF, that is, the initial voltage level supplied to the control input of microwave VCO 1 (in the transient mode preceding frequency capture), was always equal to the minimum or maximum value. This is determined by the position of the VCO frequency f of the microwave VCO output signal relative to the microwave frequency f of the microwave input signal. In this case, two main operating modes of the microwave frequency synthesizer are possible, in which synchronization in the PLL loop may be disrupted.

Let's consider the first operating mode of the microwave frequency synthesizer, shown in Fig. 3. Let us assume that the frequency f of the microwave input signal is fixed and exceeds f MF (as in the prototype), and the tuning band of microwave VCO 1 (Δf VCO) is sufficiently large, for example, significantly exceeds the value of 2 f IF. In this case, during the transient process preceding frequency capture, a mirror frequency signal from the output of microwave mixer 3 can reach the frequency-phase detector 6 (at the point of synchronization failure, at which f VCO = f 1   MF, where f 1   MF = f input microwave +f IF), which will lead to a failure of synchronization in the PLL loop, the transition of the frequency f VCO signal of the microwave VCO to the uppermost position corresponding to the frequency f VCO max and, as a consequence, to a failure in the operation of the microwave frequency synthesizer. The circuit of the microwave frequency synthesizer, chosen as a prototype, does not provide for the possibility of solving this situation. In the proposed microwave frequency synthesizer, this problem is solved as follows.

Phase comparator 11 in frequency-phase synchronization mode (f OP /m=f IF /n, φ OP =φ IF) produces a signal U FC at its output, corresponding to a logical unit (logical “1”). This output of the phase comparator 11 is connected to the input of the waiting multivibrator 12, which is triggered by a signal corresponding to logical zero (logical “0”). With an input signal equal to the log level. “0”, the first 13 and second 14 diodes are closed and the standby multivibrator 12 does not affect the operation of the PLL loop. In the case when the phase synchronization mode is violated, a signal corresponding to the log appears at the output of the phase comparator 11. "0". This can happen when the microwave frequency synthesizer is turned on or when the frequency f of the reference signal is adjusted. Signal corresponding to log. “0” from the output of phase comparator 11 triggers the standby multivibrator 12 and at its direct and inverse outputs, during the pulse duration τ m, voltage levels appear equal to log “1” and log, respectively. “0” (that is, inverse to the previous state), therefore the first 13 and second 14 diodes open and a differential voltage is supplied to the first and second inputs of the operational amplifier 9, causing the appearance of the initial (minimum) control voltage at the output of the operational amplifier 9, which is supplied respectively to frequency control input of microwave VCO 1, this sets the frequency value of the microwave VCO f VCO =f VCO min. After the end of the pulse of the waiting multivibrator 12, there is a pause equal to the value T M -τ m, where T M is the pulse repetition period of the waiting multivibrator 12. During this pause, the PLL loop adjusts the frequency f VCO of the microwave VCO signal from the minimum value f VCO min to the frequency , at which frequency-phase synchronization occurs (frequency locking point in Fig. 3). When the frequency f VCO of the microwave VCO signal is adjusted to a value at which f VCO =f MF (where f MF =f input microwave -f IF) and subject to the condition f VCO ≤f input microwave (in accordance with the phasing of PFD 6), it is established frequency-phase synchronization mode, in which f OP /m=f IF /n. At the output of phase comparator 11 a signal corresponding to the log level appears. “1”, transferring multivibrator 12 to the standby state. If for some reason the synchronization process does not occur, then the described cycle of establishing synchronization in the PLL loop is repeated. A necessary condition frequency capture, in this case, is that the pulse repetition period of the waiting multivibrator 12 must correspond to the condition: T M -τm>τ PLL loop, where

T M - pulse repetition period of the waiting multivibrator,

τ m - pulse duration of the waiting multivibrator,

τ PLL loop - time to establish synchronization in the PLL loop.

Let's consider the second operating mode of the microwave frequency synthesizer, shown in Fig. 4.

Let us assume that at the initial moment in the microwave frequency synthesizer the condition of frequency-phase synchronization is satisfied, with f input microwave = f input microwave1. In this case, the frequency of the output signal of the microwave frequency synthesizer is f MF =f MF·1 =f input microwave1 -f IF. Then the frequency f in microwave input signal is quickly adjusted in the band Δf in microwave tuning of the input microwave signal (as shown in Fig. 4) from the value f in microwave1 to the value f in microwave2 (in this case, the frequency tuning band of the input microwave signal Δf in microwave is more than 2 f IF, where f IF =f input microwave -f VCO. Simultaneously with frequency tuning f input microwave, the frequency tuning of f VCO microwave VCO occurs from the value f MF1 to the value f MF2. However, due to the inertia of the PLL loop, the frequency tuning time of the input The microwave signal (t AC microwave input) is always less than the synchronization establishment time in the PLL loop (τ PLL loop), that is, t AC microwave input ≤τ PLL loop.

As a result of the inertia of the PLL loop, when tuning the frequency of the microwave VCO, conditions also arise for disruption of synchronization. For example, as shown in FIG. 4, when adjusting the frequency f of the VCO from the initial value of f MF1 (in the upper part of the frequency tuning range of the microwave VCO) to the next lower frequency value of f MF2. in the microwave mixer, a mirror intermediate frequency signal is formed at the point where f VCO = f 1   MF2 = fin microwave 2 + f IF. In this case (with a given phasing of PFD 6), the condition f VCO ≤f microwave input will not be met, that is, the frequency is not captured by the PLL loop, which causes a violation of frequency-phase synchronization with the “dragging” of the frequency f VCO to the upper extreme value f VCO Max frequency tuning range of the microwave VCO. To restore frequency-phase synchronization in the PLL loop in the proposed invention, it is necessary to carry out the synchronization establishment cycle described in the first operating mode of the microwave frequency synthesizer. The circuit of the microwave frequency synthesizer, chosen as a prototype, does not provide for the possibility of quickly changing the frequency of the input microwave signal, and therefore, such a circuit does not allow stable phase synchronization when tuning the frequency of the input microwave signal.

The above-described modes of unstable operation of the PLL system in the well-known microwave frequency synthesizer, chosen as a prototype of the invention, were experimentally tested and confirmed.

Based on the proposed invention, samples of microwave frequency synthesizers were developed and experimentally tested, which confirmed stable operation with a fast recovery time of frequency-phase synchronization in various operating modes of microwave frequency synthesizers - less than 100 μs.

Information sources

1. Manasevich V. Frequency synthesizers. Theory and design. - M.: Communication, 1979

2. Ryzhkov A.V., Popov V.N. Frequency synthesizers in radio communication technology. - M.: Radio and communications, 1991, p. 110-113.

A microwave frequency synthesizer containing a voltage-controlled microwave oscillator (VCO), the output of which is connected to the input of a directional coupler, the first output of which is the output of the microwave frequency synthesizer, and the second output of the directional coupler is connected to the first input of the microwave mixer, the second input of the microwave mixer is connected to the output source of the input microwave signal, the output of the microwave mixer is connected to the input of the first frequency divider with a variable division ratio, the output of which is connected to the first input of the frequency-phase detector, the second input of the frequency-phase detector is connected to the output of the second frequency divider with a variable division ratio, the input of which is connected with the output of the reference signal source, and between the frequency-phase detector and the microwave VCO a low-pass filter is included, characterized in that the microwave frequency synthesizer additionally contains a phase comparator, a waiting multivibrator, two diodes and an operational amplifier, with the first and second outputs of the frequency-phase detector are connected respectively to the first and second inputs of the operational amplifier, the output of which is connected to the input of the microwave VCO, and a low-pass filter is connected between the first input of the operational amplifier and its output, the first input of the phase comparator is connected to the output of the first frequency divider with a variable division coefficient and the first input frequency-phase detector, the second input of the phase comparator is connected to the output of the second frequency divider with a variable division coefficient and to the second input of the frequency-phase detector, the output of the phase comparator is connected to the input of the waiting multivibrator, the first output of the waiting multivibrator is connected through the first diode to the first output of the frequency-phase detector phase detector and with the first input of the operational amplifier, the second output of the waiting multivibrator is connected through a second diode with the second output of the frequency-phase detector and with the second input of the operational amplifier, and the first and second diodes are connected opposite each other, while the microwave VCO, directional coupler, microwave The mixer, the first frequency divider, the frequency-phase detector, the operational amplifier and the low-pass filter form a phase-locked loop (PLL) under the condition: T M -τ m >τ PLL, where T M is the oscillation period of the waiting multivibrator, τ m is the duration pulse of the waiting multivibrator, τ PLL is the time to establish synchronization in the phase-locked loop.

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A time scale generator refers to devices that synchronize signals by frequency, phase shift and time scale. The technical result is to increase the accuracy of time scale synchronization. The time scale generator contains: a time scale receiving block, an internal quantum sequence generator, a divider, a time scale transmission block, a guard interval former, a time selector, a block of switchable delay lines, a comparator block, and a linearly varying voltage generator. 5 ill., 1 tab.

The invention relates to radio engineering and can be used in transmitting and receiving devices in the microwave frequency range. The technical result is to increase stable operation when tuning the frequency of the input microwave signal. The microwave frequency synthesizer contains a voltage-controlled microwave generator, a directional coupler, a microwave mixer, a source of an input microwave signal, a first frequency divider with a variable division coefficient, a frequency-phase detector, a second frequency divider with a variable division coefficient, a reference signal source, a low-pass filter, a phase comparator, a waiting multivibrator, two diodes and an operational amplifier. 4 ill.

The problem of frequency stability in transceiver devices has always existed. At relatively low frequencies (up to 100-150 MHz) it was solved using quartz resonators, at higher frequencies (400 MHz) - using resonators based on surface acoustic waves (SAW resonators); to stabilize ultrahigh frequencies, dielectric resonators made of high-quality material are often used. ceramics or other high-Q resonators. The described methods of stabilization using passive components have their advantages - simplicity and comparatively low cost of implementation, but their main disadvantage is the impossibility of any significant frequency tuning without changing the frequency-setting element - the resonator. The inability to quickly electronically adjust the operating frequency while maintaining its stability sharply limits the use of radio devices, not allowing, for example, the implementation of multi-channel.

Integrated frequency synthesizers from various foreign companies, which are now widely used, allow for rapid electronic tuning of the operating frequency, including ultra-high frequency, while maintaining its high stability. Such frequency synthesizers come in direct and indirect types. The advantages of direct synthesis include high performance at a small frequency grid step, but due to the need to filter a large number of spectral components caused by numerous nonlinear signal conversions, direct synthesis devices are rarely used in microwave circuits. To synthesize ultrahigh frequencies, indirect synthesizers, or phase-locked loop (PLL) synthesizers, are usually used. There are two main types of integrated synthesizers with PLL - programmable, in which the frequency values ​​are set by an external microcontroller via a three-wire bus, and non-programmable, where the division coefficients of the internal frequency dividers are fixed, and the reference frequency is set by an external quartz resonator. In simple microwave circuits, non-programmable integrated synthesizers are usually used, for example, MC12179 from Motorola, the disadvantages of which include the need to accurately select a quartz resonator, which is not always possible. Programmable frequency synthesizers, for example UMA1020M from Philips, do not have this drawback, and since modern systems communication there is always a control microcontroller present, programming such a synthesizer is technically simple. Autogenerators of the ultra-high frequency range are used in the form of functionally complete modules made using hybrid technology.

An example of the application of the described solutions is a simple laboratory ultra-high frequency synthesizer, which allows one to generate and stabilize frequencies in the range of 1900 – 2275 MHz with high accuracy, proposed in this article.

The block diagram of the designed synthesizer is shown in Fig. 1., appearance - in Fig. 2. As you can see their circuits, the synthesizer consists of a voltage-controlled oscillator (VCO or VCO) JTOS-2200 from Mini-Circuits JTOS-2200, an integrated frequency synthesizer UMA-1020M and a microcontroller Z86E0208PSC from Zilog.

The microwave signal generated by the VCO is supplied to the output of the laboratory synthesizer and to the input of the main programmable frequency divider included in the UMA-1020M circuit.

The reference signal generated by the JCO-8 quartz oscillator is fed to an auxiliary programmable frequency divider, also included in the UMA-1020M circuit. The block diagram of UMA-1020M is shown in Fig. 3, detailed technical documentation for the UMA-1020M can be found on the manufacturer’s website http://www.philips.de/. The coefficients of both dividers - the main and auxiliary - are set by the Z86E0208PSC microcontroller via a three-wire (DATA data, CLK synchronization and write permission / ENABLE) bus. The block diagram of the Z86E0208PSC microcontroller is shown in Fig. 4. The internal ROM of the microcontroller is sufficient to program seven different meanings frequencies and one test mode. Specific frequency values ​​(or test mode) are set by jumpers on the printed circuit board of the laboratory synthesizer. Before loading the next frequency value into the integrated synthesizer, the microcontroller polls the port connected to the jumpers and, in accordance with the received data, selects one or another firmware. The new frequency value is set automatically when the synthesizer board is powered on. The synthesizer programming algorithm for the Z86E0208PSC microcontroller is shown in Fig. 5, the program listing is given.

More details about programming Zilog microcontrollers can be read in, complete technical documentation is available on the website http://www.zilog.com/.

A special feature of the JTOS-2200 VCO used is the tuning voltage range: from 0.5 to 5 Volts. That is, if the setting voltage value is less than 0.5 Volts, the manufacturer does not guarantee stable generation of oscillations. The experiments carried out showed the veracity of this statement.

The operating principle of the PLL, as well as the methodology for calculating the feedback filter (Loop filter), are quite widely and repeatedly discussed in the technical literature, so they are not discussed in this article. There are several freely available programs that allow you to calculate feedback filter parameters and can be found on the Internet at http://www.analog.com/ or at www.national.com.

To monitor the correct operation of the synthesizer circuit, an LED is installed on the board, the glow of which indicates an error in frequency synthesis. When the synthesizer is working correctly, the LED should not light up, but this function can be disabled by software.

The cost of the assembled laboratory synthesizer does not exceed $30. To reduce the cost of the proposed device, two ways can be proposed: firstly, you can combine the quartz reference oscillation source of the synthesizer and the microcontroller, while remembering that the maximum clock frequency of the Z86E0208PSC is 8 MHz, while for the UMA-1020M it can be within 5-40 MHz. Secondly, VCOs can be developed independently using transistors or amplification integrated circuits using the methodology given in.

List of used literature

1. Dielectric resonators / M.E. Ilchenko, V.F. Vzyatyshev, L.G. Gassanov et al.; Ed. M.E. Ilchenko. – M.: Radio and Communications, 1989. – 328 p.: ill. – ISBN 5-256-00217-1.
2. Pestryakov A.V. Integrated circuits for synthesis and frequency stabilization devices // Chip News. – 1996. - No. 2.
3. Lobov V., Steshenko V., Shakhtarin B. Digital synthesizers for direct frequency synthesis // Chip News. – 1997. - No. 1.
4. Wireless Semiconductor Solutions. Motorola. Device Data – Vol.1. DL 110/D, Rev 9.
5. VCO Designer's Handbook 2001. VCO/HB-01. Mini-Circuits.
6. Gladstein M.A. Microcontrollers of the Z86 family from Zilog. Programmer's Guide. - M.: DODEKA, 1999, 96 p.
7. The Z8 Application Note Handbook. Zilog. DB97Z8X0101.
8. Starikov O. PLL method and principles of synthesizing high-frequency signals//Chip News. – 2001. - No. 6.
9. Microwave Oscillator Design. Application Note A008// Hewlett-Packard Co. - publication number 5968-3628E (6/99)
10. Shveshkeyev P. A VCO Design for WLAN Applications in the 2.4 to 2.5 GHz ISM Band//Applied Microwave&Wireless. – 2000. - No. 6. – P.100-115.

As follows from § 1.10, in principle it is possible to build a DKSCH system using digital phase-locked loop in any frequency range, including microwave. Well-known publications about such systems, although only in the decimeter range (for example, , ), date back to the second half of the 60s. As for the SMV range, we know of only one article from 1971, which describes a digital synthesizer in this range. Let's agree that synthesizers in the range up to 400 MHz belong to the meter wavelength range, to which they are closer not only because they cover a range that is only slightly larger than the meter limit, but also according to the principles of their construction.

Since the width of the operating frequency range of the simplest digital synthesizer cannot exceed the maximum speed of the DPCD, practically the simplest DLL systems are not applicable to microwaves. It was noted above that turning on the DPKD before the DPKD makes the system more inertial and worsens the noise characteristics of the latter. Indeed, if the maximum speed of modern DPCDs is approximately 50 MHz, then for f 0 = 5 GHz (the middle of the centimeter range) a DPCD with a division factor c = 100 is required, i.e., other things being equal, the band of the DPLLL ring narrows from this in this example by two orders of magnitude.

As was shown in § 1.10, the heterodyning DFLL system (Fig. 1.12c), although more bulky, has electrical characteristics that are not inferior to the simplest system. It is not limited by the speed of the DPKD and, therefore, can be used in microwave synthesizers. However, the use of this system in microwaves has its own characteristics. Firstly, since the width of the operating frequency range P 0 = f 0 max - f 0 min at microwave almost always exceeds the speed of the DPKD f DP max, heterodyning should be carried out not by one frequency, but by a grid of reference frequencies f q (k) (as in the older decade multi-decade DKSCH system). Secondly, the discreteness step of the specified grid β k should not exceed the width of the range of stable division of the DPKD f DP max - f DP min, i.e. practically β k f DP max - f DP min, then before the DPKD you will have to turn on the DPKD in the form of one or two triggers. Such a small division factor of the DPKD (c = 2 or c = 4), firstly, will not noticeably deteriorate the electrical characteristics of the system and, secondly, as the industry develops faster-acting DPKDs, the DFKD will first degenerate into a single trigger (c = 2), and then can be completely excluded from the scheme.

Thus, a typical microwave block diagram of a digital synthesizer can be depicted as shown in Fig. 3.1a. For this system

The joint solution of (3.1) and (3.2) gives

Then from (3.3) and (3.4) the division coefficient of the DPKD

In the second chapter, the criteria [form (2.44)] for selecting reference frequencies were defined, ensuring the absence of side components uncontrolled by the PLL ring at the output of the synthesizer. Let's see how these criteria are met in the diagram in Fig. 3.1a. Because

then, substituting (3.6) into (3.1), we obtain

From (2.44) it follows that it is necessary to fulfill the condition If we take the extreme case in the last expression (replace inequality with equality) and, taking this into account, substitute (3.8) into (3.7), then it turns out that

However, as a rule, in microwave systems P 0 >> f DC max. Therefore, either the DFCD division coefficient must be chosen sufficiently large, or condition (2.44) in the system of Fig. 3.1a can only be fulfilled in a special case.

Here it was accepted that, however, one can come to the same conclusions.

The negative influence of DFCD on the system parameters was shown above, especially at large c. One cannot count on a sharp increase in the performance of the DPKD in the near future. Therefore, the system Fig. 3.1a can only be used in a narrow-band synthesizer.

Since the fulfillment of one of the inequalities (2.44) should be considered mandatory, it is necessary to transpose the reference frequencies f" q "up" or "down" beyond the operating range of the synthesizer, and if the synthesizer operates on a receiver or transmitter mixer, then beyond the operating range of the carriers frequencies of the radio link. In this case, as is obvious, conditions (2.44) must be supplemented with one more inequality