Types of data interfaces. Serial data interfaces. Main types of data interfaces

LAB #13

Standard data interfaces of computer systems

Goal of the work. Acquaintance with the main data transmission interfaces of computer systems.

Exercise:

1. Familiarize yourself with the main interfaces.

2. Determine the basic parameters of the interfaces (interrupts, I / O ports, DMA, data exchange rate).

BASIC INFORMATION

An interface is a communication device (or protocol) that allows one device to communicate with another. Sets the correspondence between the output of one device and the input of another.

With the advent of USB (Universal Serial Bus), the relics associated with the ISA bus architecture from the time of the first IBM PC are gradually becoming a thing of the past: COM and LPT ports, the FDD connection interface. Chipsets motherboards, which do not explicitly support the ISA bus, now occupy the lion's share of the market. Almost all modern chipsets support the USB interface, including the new 2.0 specification. The USB architecture provides for the topology of the so-called "star". That is, the system must have a root (master) hub, to which peripheral hubs are connected, and to the latter - USB devices. Peripheral hubs can be connected to each other, forming cascades. A total of 127 devices (hubs and USB devices) can be connected through one root hub. However, given the relatively low throughput bus version 1.0 (up to 12 Mbit per second), which, taking into account service costs, will be about 1 Mbyte per second, 4-5 devices should be considered the optimal number. However, it is recommended to connect faster devices closer to the root hub. The problem of low bandwidth is removed with the introduction of the USB 2.0 interface specification, whose peak performance reaches 480 Mbps. This value is quite enough for typical USB devices: printers, office scanners, digital cameras, joysticks and others. But still, external drives, high-end scanners, digital video cameras require a faster interface, such as SCSI.

The USB specification defines two parts of the interface: internal and external. The internal part is divided into hardware (the root hub itself and the USB controller) and software (drivers for the controller, bus, hub, clients). The external part is represented by USB devices (hubs and components). To ensure correct operation, all devices are divided into classes: printers, scanners, drives, etc. Device classes and features of their functioning are described in detail in the USB specification. If you deviate from these requirements, you may experience problems loading drivers and connecting devices. On the contrary, strict adherence to the specification allows third-party software manufacturers to create drivers for any device. The division of devices into classes occurs not according to their intended purpose, but according to a single way of interacting with the USB bus. Therefore, the printer class driver does not determine its resolution or color, but the method of transmission (unilateral or bidirectional) and data formatting, the order of initialization when connected. USB data is transferred in various formats. The simplest way is to send a stream of bytes with a token. In this case, the token travels in the direction of the root hub from device to device, and data is transferred when there is free bandwidth. The guaranteed bandwidth is provided by the isochronous format. In this case, synchronous devices are polled at the rate required by the bandwidth. The clock frequencies of the receiver and transmitter are also synchronized. Isochronous mode is most often used to connect audio devices that require a constant bandwidth. The interrupt format is used for devices that operate in real time until the desired event occurs. Such devices are polled at a fixed frequency, and data is transmitted when a signal is received about an event. The management format is specific and is used to configure and manage hubs and devices. The procedure for connecting peripherals to the USB bus occurs "in hot mode". A device connected to a free port causes a voltage drop in the circuit. The controller immediately forwards the request to this port. The attached device receives the request and sends a class data packet, then it is assigned a unique identification number. Next, the device driver is automatically loaded and activated, configured and, thus, the final connection. Everything, the device is ready to work! In the same way, the device already connected and included in the network is initialized.

Graphic designation

PS/2 port

Named after the IBM PS/2, these connectors are widely used today as standard keyboard and mouse interfaces, but they are slowly being replaced by USB.

In personal computers, starting with AT, the keyboard is connected via a connector to a special controller (UPI-Universal Peripheral Interface) on the motherboard. The keyboard itself contains a microcontroller that is connected via a serial link to a universal peripheral interface chip. Data is transmitted over the channel in packets of 11 bits, of which 8 bits are reserved for the actual data, and the rest for synchronizing and control signals. Note that the keyboard's serial interface is not compatible with the RS-232C serial interface. The chip contains its own RAM and ROM. The controller installed in the keyboard, when pressing the key, determines the coordinates of the closed contact in the matrix and transmits the so-called "scan code" to the controller. In turn, the controller converts the received scan code and sends it to the processor. For this operation, the interrupt request line IRQ1 is used exclusively. The PS / 2 interface differs from AT only in the connector and the controller installed on the system board. The PS/2 interface uses a +5 V unipolar signal. Data transfer occurs in synchronous mode. Since a regular RS-232C serial mouse is asynchronous and uses a bipolar signal for power, it is not compatible with the PS/2 port. Attempting to connect an RS-232C mouse through an adapter to the PS/2 port may damage the mouse. Thus, only a keyboard can be connected to the PS / 2 connector through an adapter, as well as those RS-232 mice that are equipped with a special adapter.

IDE interface (ATA)

Over the long history of the development of the IDE interface (Integtated Drive Electronics - electronics integrated into the drive), many designations of its standards have appeared. Let's start with the already distant 80s, when IBM released an AT (Advanced Technology) specification computer. The hard drive of this computer was connected to the 16-bit ISA bus and controlled by its own controller. The largest manufacturer of hard drives, Western Digital, offered to build control electronics into the hard drive itself. The agreed standard for such an interface was called ATA (AT Attachment - connection to AT) and provided the ability to upgrade by simply replacing (or adding) hard drives. A little later, the designation of the same IDE interface appeared. Nowadays, the abbreviation IDE often means in general all devices compatible with the ATA interface “top down”: Fast ATA, EIDE, Ultra ATA and others. The ATA specification defined that two devices (Master and Slave) can be connected to one channel. Set the communication modes PIO (0, 1, 2, 4, 5) and DMA (SW 0, 1. 2 and MW0).

The PIO mode (Programmed Input-Output - program input-output) provides for the participation of the central processor in the exchange of data between the disk and RAM. In DMA (Direct Memory Access - direct memory access) mode, the device directly communicates with the system memory, intercepting control of the bus. The SW (Single Word) and MW (Multi Word) protocols determine how data is transmitted. The mode numbers indicate the duration of the exchange cycle and thus the data rate (eg 1 - 240 ns, 2 - 180 ns). In abbreviated form, this is usually written like this: SW2 DMA. MW1 DMA, PIO2, etc. The 16-bit addressing of the ISA bus did not allow hard disks larger than 528 MB to be supported.

The ATA interface could not provide connections for any other devices other than hard drives. Meanwhile, new components appeared: CD-ROM drives, magneto-optics, streamers, each of which was equipped with its own interface from the manufacturer and usually required a unique expansion card connected to the ISA slot, incompatible with other devices. In addition, the speed of hard drives has grown significantly, and the modes provided by ATA no longer meet modern requirements. This is how the standard for the ATA-2 interface appeared, which established faster PIO (3 and 4), MW DMA (1 and 2) protocols, defined a new data exchange mode Block transfer (transfer in blocks) and disk space addressing LBA (Logical Block Addressing - logical block addressing). In addition, the disk identification commands that provide information on system requests about the characteristics of the device have been expanded. As already mentioned, the IDE / ATA interface, even in the latest implementations, remains 16-bit. The PCI bus, to which the IDE controllers of the motherboard chipset are connected, is 32-bit. Therefore, the controller makes one 32-bit packet from two consecutive 16-bit packets and sends it further along the bus. It is clear that even in the fastest mode, a 16-bit packet sent from the hard disk slows down the system. That is why SCSI drives are preferred for high-performance devices. In 1997, the next ATA-3 standard was adopted, which actually had, in comparison with ATA-2, the only new element- the so-called S.M.A.R.T. (Self-Monitoring Analysis and Reporting Technology - self-testing and analysis technology). In terms of data exchange modes, ATA-3 fully corresponds to ATA-2. A significant step forward in the development of the interface was the emergence of the ATAPI protocol (ATA Packet Interface - ATA packet interface). It provided an IDE connection for components other than hard drives. At the same time, from the user's point of view, there was no difference in access to devices of various types. The ATAI protocol requires appropriate support from the BIOS, and latest versions The BIOS can designate any device connected via the ATAPI protocol as bootable. The protocol was included in the new ATA/ATAPI-4 standard approved in 1998.

Data exchange protocols have also been supplemented with new standards: Ultra DMA mode 2 and error correction mode by checksum (CRC - Cyclic Redundancy Check). In addition, multitasking modes have appeared, that is, modes of parallel execution of commands and the creation of queues by two devices on the same IDE channel (though with significant limitations). ATA/ATAPI-4 hard drives were produced under the designation Ultra ATA-33. Sufficiently harmonious and complete system of ATA interfaces, described above, did not fail to confuse manufacturers of hard drives and other storage media competing with each other. In order to distinguish their products in the market, they came up with their own interface names. Seagate was the first to take this path and came up with the name Fast ATA. In fact, its product differs from ATA-2 just by the absence of the fastest exchange modes (PIO4 and MW2 DMA). Quantum "invented" the name Fast ATA-2 for its interface, which is essentially the same as the ATA-2 standard. Most of all, the situation was confused by Western Digital, which came up with the designation EIDE (Enhanced IDE - improved IDE). This term is still widely used in the computer industry. If you try to determine the differences between EIDE and ATA-2, then surprising things turn out. It turns out that EIDE fully includes all the ATA-2 specifications and the ATAPI protocol. Thus, the expression "hard disk with EIDE interface" is equivalent in meaning to the phrase "hard disk with ATA-2 interface". So how is EIDE different? The fact is that WD came up with a Dual IDE / ATA host adapter that allows you to use up to four devices. However, such an adapter has nothing to do with the IDE interface standard itself and is an external device for any IDE / ATA component that provides normal functioning according to the standards.

In 1999, the ATA/ATAPI-5 standard was adopted, and most manufacturers supported it with real products. The Ultra ATA-66 protocol of the new standard stipulated a data transfer mode at speeds up to 66 MB / s (Ultra DMA mode 4 specification). To connect such drives, new cables (with alternating signal conductors and lines shorted to ground) were needed, having 80 conductors, compatible, fortunately, with existing 40-pin IDE connectors. Multi-vendor research has further expanded the bandwidth of IDE devices using the new 80-wire cable. This is how the ATA/ATAPI-6 specification appeared, which defines the requirements for hard drives and an interface with a peak bandwidth of up to 100 MB/s (Ultra DMA mode 5). In particular, an increase in LBA from 32 to 64 bits is provided. Support for special streaming video transmission modes, measures to reduce disk noise. Hard disks with ATA/ATAPI-6 interface are widely represented now and are usually referred to by sellers as ATA-100. The possibilities for further improvement of the parallel IDE interface, despite the appearance of UltraATA-133 hard drives, are practically exhausted, and therefore the serial Serial ATA interface is considered as a promising direction.

The official specification for Serial ATA appeared in 2002, and a year earlier, the first hard drives with a new interface were introduced. Chipsets on motherboards with Serial ATA support first saw the light of day in the fall of 2002. Legacy motherboards require a separate controller installed in the PCI slot, which means performance is limited.

The main difference of the new interface is a fundamentally different - sequential - way of data exchange. Data is transmitted over an eight-core cable, the signal level is 3.3 V. To date, the implementation of the interface allows reaching a peak bandwidth of 1.5 Gb / s (approximately 187 Mb / s), but the developers promise to double this figure in the near future. Thus, finally, the bandwidth of the external interface will correspond to the speed of internal data transfer (between the disk itself and the buffer) of hard drives. In the summer of 2000, Seagate was the first to introduce a hard drive with a Serial ATA interface.

PCI interface

PCI (Peripheral Component Interconnect) - connection of external components. The development of the PCI interface took place in the spring of 1991 in the bowels of Intel Corporation. Promising 80486 and Pentium processors required a new organization of interaction with peripheral components. Intel engineers decided to start from scratch and as a result developed a bus that is not directly connected to the system bus. So it was possible to ensure the independence of the interface from a specific type of processor and its parallel operation with several PCI devices. The new interface turned out to be incompatible with any of the previous ones (ISA, VESA) and required the development of a system chipset. In order to provide third-party support, Intel made the PCI architecture and specifications open, so a group of interested organizations soon formed and approved the version 2.1 specification. The refined and improved specification was designated 2.2. The PCI interface provides a 33 MHz bus clock (PCI 2.2 variant up to 66 MHz, PCI-X up to 133 MHz), which provides peak throughput up to 132 MB/s (up to 1064 MB/s for 64-bit data at 133 MHz). MHz).

The interface provides support for Bus Mastering mode and automatic component configuration during installation (Plug-and-Play). All PCI slots on the motherboard are grouped into segments, the number of slots in a segment is limited to four. If there are several segments, they are connected by means of so-called bridges. Currently, PCI is the most common interface. With its help, expansion devices are connected to the motherboard: sound cards, SCSI controllers, modems, video capture cards, network cards and other components.

PCI's continued popularity is due to a number of advantages the interface provides over its predecessors.

· Firstly, synchronous data exchange of 32 or 64 bit format is supported. In this case, the multiplexing method is used (transfer of addresses and data in turn over one line), which made it possible to reduce the number of contacts in the connectors.

· Secondly, the installation of components with signal levels of 5V or 3.3V is provided. "Keys" (plastic jumpers) on the connectors exclude the installation of boards in a "foreign" slot. It is possible to manufacture universal expansion boards that support both levels of signals (which is what most manufacturers do now).

The combination of 33 MHz or 66 MHz bus frequencies with data width provides a wide enough range to select the bus bandwidth. Note that at 66 MHz, only 3.3V is acceptable (and 33 MHz devices may fail at higher frequencies).

The PCI specification requires components to support Multiple Bus Mastering (multilateral bus management). In this mode, devices take control of the bus and allocate its resources on their own. A special timer, available on the device, determines the maximum time during which exclusive access is possible.

One PCI controller channel supports up to four expansion slots. To double their number, a bridge is used between a pair of controllers. The bus data transfer method is called Linear Burst. That is, when writing-reading data goes in a single package, since the address for each next byte automatically increases by one. This eliminates the need to transmit an address block. To speed up the transfer, caching is used: methods of delayed “write-back” and end-to-end “write-through” recording are supported.

An important feature of the PCI interface is Plug-and-Play (PnP) support. Specification 2.2 defines three types of resources: memory range, I/O range, and the so-called "config space". The last resource contains three regions: header (does not depend on a specific device type), device block, user block. The header contains information about the manufacturer, device class, and other service information.

In general, the PCI interface coped with the tasks assigned to it within the limits of its inherent limitations. The same tasks that he could not solve (for example, transferring large arrays of graphic data at high speed) were cleverly transferred by Intel to other interfaces (for example, AGP).

Until recently, the PCI bus was used not only for expansion cards, but also connected the bridges of the system chipset. However, significant restrictions on peak bandwidth began to slow down the growth of computer system performance. In particular, the advent of ATA-100 specification hard drives, Gigabyte Ethernet network cards, Ultra 160 specification SCSI adapters required an increase in the PCI bus bandwidth by several times. Attempts to improve the bus resulted in the adoption of the PCI-X specification.

64-bit PCI-X specification interface slots (supporting clock speeds up to 133 MHz and data transfer via DDR and QDR protocols) are still found only on high-performance servers and workstations, since an increase in bus width and its operating frequencies has led to a significant increase in the cost of the motherboard . At the same time, the very principle of a parallel shared bus has already become obsolete.

Thus, the lifetime of the PCI bus on the PC platform is gradually expiring. There is nothing unusual in this - a similar story happened with the ISA bus, which is no longer found on modern motherboards. Obviously, the transition to the new local bus will be gradual and relatively painless for the average user. Currently, the main contenders are the PCI Express interface (3GIO) developed by Intel Corporation and the HyperTransport bus offered by AMD. Moreover, HyperTransport is already supported by many chipsets.

HyperTransport Interface

The HyperTransport (HT) high-speed I/O bus is intended for use in computer systems, primarily as an internal local bus. Compared to the PCI bus, the HyperTransport interface reduces the number of conductors on the motherboard, eliminates the delays associated with bus monopolization by low-performance devices, reduces power consumption, and generally increases throughput by a factor of many.

Physically, HyperTransport technology is based on an improved version of Low Voltage Differential Signaling (LVDS). All lines (data, control, clock) use 100 ohm differential busses. The signal level is 1.2V (as opposed to the 2.5V set by the IEEE LVDS specification). Due to this, the bus length can reach 24 inches (about 61 cm) with a bandwidth of up to 800 Mbps on a single line. It should be noted that the HyperTransport specification provides for the separation of "upstream" (Upstream) and "downstream" (Downstream) data streams (asynchrony). This approach allows a significant increase in clock speeds compared to existing architectures, since each LVDS signal operates within its physical line. In addition, a packet that combines addresses, commands, and data is always a multiple of 32 bits. Therefore, its error-free transmission is ensured over scalable channels with a width of 2 to 32 bits. This makes it possible to use a single HyperTransport technology to connect bus resource consumers of different performance: processor, RAM, video controller, low-speed I/O devices, using the minimum required number of lines in each case. In general, the peak throughput of the Hyper Transport connection reaches 12.8 GB / s (6.4 GB / s for downlink and uplink 32-bit wide at 800 MHz and data transmission on the rise and fall of the signal). For comparison, we indicate that the peak bandwidth of the system bus (200 MHz) AMD processor Athlon is 2.128 GB/s. An important feature of HyperTransport technology is compatibility with PCI devices at the protocol level. That is, equipment manufacturers do not even have to write new drivers.

SCSI Interface

The SCSI interface (read - "tell me") is often compared exclusively with the IDE interface. In fact, such a comparison is not entirely correct: SCSI, unlike IDE, allows you to connect not only storage media. SCSI is a universal interface and until the advent of IEEE1394 there was practically no alternative to it in working with high-speed devices. Today, the maximum (theoretical) data transfer rate on the IDE bus is 133 MB/s (Ultra ATA-133 protocol), for the new Serial ATA interface - up to 150 MB/s. The Ultra320 SCSI specification provides for an exchange rate of up to 320 MB/s. The real benefits of SCSI are especially noticeable in multitasking operating systems and in the processing of continuous streams of data (eg, video). Many well-known manufacturers (in particular, Iwill) release motherboards with integrated SCSI controllers, which require their own SCSI BIOS for initialization. On motherboards with an integrated controller, it is usually present in the system BIOS as an add-on. Expansion boards have their own BIOS chip. It is also possible (in the cheapest systems) that there is no BIOS and that the interface is supported exclusively by operating system drivers.

The standard functions of the SCSI BIOS are very similar to those of the system BIOS:

setting up the adapter configuration;

check the surface of hard drives;

Low level formatting

setting device initialization parameters;

setting the number of the boot device;

Choice of boot device, etc.

To memorize and store the configuration of SCSI devices, a flash memory chip (a functional analogue of the motherboard CMOS) is used. In a SCSI system, communication between devices is carried out on a sender-to-destination basis. The sender initiates a request and, after waiting for a response from the addressee, begins the data exchange. Each device in the chain has a unique identification (ID) number ranging from 0 to 7 (in the latest specifications from 0 to 31), which is set by a special switch, jumper, or assigned automatically (in modern devices). Moreover, number 7 is assigned by default to the SCSI host adapter. In turn, devices included in the component that has an ID receive a logical unit number - Logical Unit Number (LUN). For example, if you connect an array of multiple hard drives, it will get its own ID, and each hard drive will get its own LUN. In this way, you can chain up to 256 devices. Although in real problems such constructions are unlikely to be required. Data on the SCSI bus is transmitted in synchronous or asynchronous modes. In asynchronous mode, the addressee acknowledges the receipt of each byte, in synchronous mode, only the data packet. Starting with the SCSI-2 specification, scenarios have appeared when the entire set of exchange procedures is formed into one packet and transmitted as a whole. It is also possible for the device to execute commands independently. For example, the streamer is given a command to rewind, and then it is disconnected from the bus before the end of the process. Currently, there are several SCSI specifications that differ in bus width, clock frequency, and physical type of connection interface. The very first variant (SCSI-1) had an 8-bit bus, over which data was transferred at a rate of 5 MB/s. The latter, Ultra320 SCSI, allows you to transfer data at a speed of 320 MB / s.

Unfortunately, the difference in standards for the level and format of signals, the electrical characteristics of SCSI devices in different interface specifications make it very difficult to connect components of different generations. Although in principle this problem can be solved in the vast majority of cases.

AGP interface

Intel, having discovered that a further increase in the performance of a personal computer “rests” on the video subsystem, has long ago proposed to allocate a separate interface bus for transmitting a video data stream - AGP (Accelerated Graphics Port - an accelerated graphics port). Literally in a year, this standard replaced the previously existing interfaces used by video cards: ISA, VLB and PCI. The main advantage of the new bus was its high throughput. If the ISA bus allowed transfers up to 5.5 MB / s, VLB - up to 130 MB / s (however, it overloaded the central processor), and PCI up to 133 MB / s, then the AGP bus theoretically has a peak bandwidth of up to 2132 MB / s. s (in 32-bit word transmission mode).

Intel developed the AGP interface to solve two main problems associated with the processing of 3D graphics on a personal computer.

· Firstly, 3D graphics require as much memory as possible to store texture data and Z-buffer. The more texture maps available for 3D applications, the better the picture looks on the monitor screen. Usually, the same memory is used for the Z-buffer as for textures. Video controller developers used to be able to use ordinary RAM to store information about textures and the Z-buffer, but the bandwidth of the PCI bus was a serious limitation here. The PCI bandwidth was too small for real-time graphics processing. Intel solved this problem by introducing the AGP bus standard.

· Secondly, the AGP interface provides a direct connection between the graphics subsystem and RAM. Thus, the requirements of real-time 3D graphics output are met and, in addition, the frame buffer memory is used more efficiently, thereby increasing the processing speed of 2D graphics. In effect, the AGP bus connects the graphics subsystem to the system memory controller, sharing access with the computer's CPU. Through AGP, it is possible to connect the only type of device - graphics cards. At the same time, video controllers built into the motherboard and using the AGP interface cannot be upgraded. For an AGP controller, the specific physical address where information is stored in random access memory, doesn't matter. This is a key decision of the new technology, providing access to graphic data as a single block of memory.

The AGP specification is actually based on the PCI version 2.1 standard, but differs from it in the following main features that radically affect performance:

The bus is capable of transmitting two (AGP2x), four (AGP4x) or eight (AGP8x) data blocks in one cycle;

Multiplexing of address and data lines has been eliminated (in PCI, to reduce the cost of motherboards, address and data are transmitted over the same lines);
pipelining of read/write operations, according to the developers, eliminates the impact of delays in memory modules on the speed of these operations.

The AGP bus supports all standard PCI bus operations, so the data flow through it can be thought of as a mix of interleaved AGP and PCI read/write operations. The AGP bus operations are split. This means that the request for an operation is separated from the actual data transfer. This approach allows the AGP device to generate a request queue without waiting for the current operation to complete. Version AGP 2.0, due to the use of low-voltage electrical specifications, provides for the implementation of four transactions (data block transfers) per cycle (AGP4x mode). Version AGP 3.0 provides for the transfer of eight blocks of data per cycle (AGP 8x mode). Currently, although even the possibilities of AGP4x are not yet exhausted by many video cards, Intel is promoting a new specification - AGP Pro. The main difference of this interface is the ability to manage a powerful power supply.

By the end of 2002, chipsets supporting the AGP version 3.0 interface (sometimes referred to as AGP 8x) appeared in mass quantities. A twofold increase in throughput was achieved by increasing the bus clock frequency to 66 MHz and using a new signal level of 0.8 V (AGP 2.0 used a level of 1.5 V). Thus, while maintaining the basic parameters of the interface, it was possible to increase the bus throughput to approximately 2132 MB / s.

In connection with the ever-widening penetration of 3D graphics into various software products, in the foreseeable future, the question arises of increasing the bandwidth of the video card bus. Applicants to replace AGP are new universal local bus interfaces: HyperTransport and PCI Express.

Bluetooth

A single Bluetooth system consists of a module that provides radio communication, and a host attached to it, which can be a computer or any peripheral device. Bluetooth modules are usually built into the device, connected through an available port or a PC card. Since all modules are physically and functionally equivalent from the point of view of the network, the nature of the host can be abstracted away. The module consists of a link manager, a link controller and a transceiver with an antenna. Modules can both be connected according to the "point-to-point" scheme, and provide multipoint connections. Two radio-linked modules form a piconet. Moreover, one of the modules plays the role of a master (master), the second - a slave (slave). A piconet cannot have more than eight modules: the address of the active piconet member used for identification is three bits. Seven slave modules can have a unique address (the master has no address), and address zero is reserved for broadcast messages. To combine more than eight devices, the concept of a scatternet (scatternet, scattered network) is introduced into the specification. The scatternet is formed from several independent piconets. Any network module, including the master one, can establish communication with a module connected to another piconet.

The optimal range of the module is up to 10m. Operating frequency range 2.402-2.483 GHz. The Bluetooth communication channel has a peak bandwidth of 721 Kbps. To reduce losses and ensure compatibility of piconets, the frequency in Bluetooth is hopped (1600 hops / s). The channel is divided into time slots (intervals) with a length of 625 ms (time between hops), in each of them the device can transmit an information packet. For full duplex transmission, TDD (Time-Division Duplex) is used. On even values ​​of the timer, the master device starts to transmit, on odd values ​​- the slave.

In addition to the payload, the packet contains an access code and a header. There are three types of packets: voice-only (usually 64 KB/s), data-only, and combined. Two types of connections are provided for the transmission of different packets: asynchronous ACL (Asynchronous Connection-Less) and synchronous SCO (Synchronous Connection-Oriented). different couples master-slave within a piconet can use different types of communication. Moreover, the type of communication can be changed as needed without any restrictions during the communication session.

OPERATING PROCEDURE

Right-click on the My Computer icon, and then select Properties from the drop-down menu. Before us appears System Properties, where we select the Hardware tab. In the tab that appears, click the Device Manager button. A window appears in front of us, which contains a list of all installed equipment on this computer, you can immediately change the properties of any device. An example of a device manager is shown in fig. 1.

1. IDE ATA/ATAPI controllers are devices that control other devices, such as a hard drive or CD-ROM, and also support the exchange of data between these devices and a computer.

The controller configuration provides for the allocation of system resources necessary for it.

Almost every developer has faced the task of developing data exchange devices to one degree or another. In the case of choosing a protocol for a new product, there is always a question of a trade-off between the complexity of the interface hardware (“munitions”) and the data transfer protocol (“constitution”). In addition, looking closely at the newfangled interface, we should not forget that very often in our modest tasks the capabilities of the good old RS232 or RS485 are sufficient, the implementation of which is also extremely cheap and has been worked out many times.

The last few years, in addition to other delights, have brought the developer a whole bunch of new interfaces that allow you to transfer large amounts of information over a considerable distance without interference. Modern FPGAs from leading manufacturers have built-in hardware implementation of such interfaces as GTL, LVDS. However, almost the entire modern element base of signal processing devices is designed to operate from a supply voltage of no higher than 3.3 V, which necessitates the development of methods for pairing these interfaces with traditional ones. At the same time, there is practically no literature on this issue in Russian. Many companies have published guides on the use of IP for the implementation of interface hardware, but, unfortunately, they are not always available to the Russian reader.

Rice. 1. Fields of application of data interfaces

On fig. 1 shows the areas of use of various data transmission interfaces in the coordinates distance - transmission speed.

As it is easy to see, if information is required to be transmitted over a distance of more than a few tens of centimeters, the standard logical levels turn out to be unsatisfactory. Specialized protocols come to the rescue. Which one to choose for the developed system? What element base will allow to implement it in hardware? What are the features of using this interface? These questions will be answered in this lesson.

When choosing a data transfer protocol, you should pay attention to several basic parameters. These are the data transfer rate, the distance between the data source and the receiver, predetermined signal levels, compatibility, the type of interface (parallel or serial). In table. 1 shows a brief description of the main interfaces and data on the main manufacturers of ICs that support them. Of course, the last column reflects only a small fraction of existing solutions - in cases where there are too many manufacturers, the table modestly indicates the IC family.

Table 1. Data interfaces

According to the method of organizing data transfer, single-wire (single-ended) and differential (differential) interfaces are distinguished. On fig. Figure 2 shows a generalized diagram of a single-wire interface In single-wire data transmission, one signal line is used, and its logic level is determined with respect to ground. For simple slow interfaces, a common ground is acceptable. In more advanced interfaces, each signal wire has its own ground, and both wires are usually combined into a twisted pair. The advantage of single-wire systems is the simplicity and low cost of implementation. Because each data line requires only one signal wire, they are convenient for transmitting parallel data over short distances. An example is the familiar parallel printer interface. Another example is the RS-232 serial interface. As you can see, single-wire interfaces are often used in cases where the decisive factor is the cost of implementation.

Rice. 2. Single wire interface

The main disadvantage of single-wire systems is their low noise immunity. Due to pickups on the common wire, a shift in signal levels is possible, leading to errors. When transmitting over distances of the order of several meters, the inductance and capacitance of the wires begin to affect.

These shortcomings can be overcome in differential systems. On fig. 3 shows a schematic diagram of the implementation of differential data transmission.

Rice. 3. Differential interface

A pair of wires is used for balanced differential data transmission. At the receiving end of the line, the difference between the signals is calculated. Note that this method of data transmission is suitable not only for digital, but also for analog lines. It is clear that with differential transmission it is possible to suppress the common-mode interference to a large extent. This implies the main advantage of differential protocols - high noise immunity. No wonder one of the most common protocols in industrial computers - RS-485 is built according to a differential scheme.

The disadvantage of differential circuits is their relatively high cost, as well as the difficulty in making paired matched cascades of transmitters and receivers.

Consider the physical parameters of the interfaces. The following designation of levels is accepted in the literature.

• VIH - high level input voltage (logic unit);
• VIL - low level input voltage (logic zero);
• VOH - high level output voltage (logic one);
• VOL - low level output voltage (logic zero).

On fig. 4 shows logic levels for single-wire interfaces, and fig. 5 - for differential.

Rice. 4. Signal levels in single-wire interfaces

Interface TIA/EIA- 644 (LVDS - Low voltage differential signaling), used in high-speed data transmission systems. The LVDS interface uses differential data transmission with fairly low signal levels. The signal difference is 300 mV, the lines are loaded with a resistance of 100 ohms. The output current of the transmitter is 2.47 to 4.54 mA. The TIA/EIA - 644 interface has the best performance consumption compared to TIA / EIA - 422 and can serve as its replacement in new developments. Max Speed data transfer is 655 Mbps. The advantage of this interface is the succession of transceiver ICs in terms of wiring with drivers of well-known and used RS-422 and RS-485 interfaces. This approach allows the use of new interfaces in already developed boards, which facilitates the transition to a new element base.

Interface LVDS support many modern FPGAs, such as ALTERA's APEX, Xilinx's Virtex, and a number of others. Typical representatives of drivers for this interface are ICs SN65LVDS31/32, SN65LVDS179 from Texas Instruments.

According to the electrical properties, the LVDS interface is adjacent to the interface LVDM. This protocol is supported by ICs SN65LVDM176, SN65LVDM050.

Rice. 5. Signal levels in two-wire interfaces

When designing single-wire interfaces, one of the central problems is the interface of various devices with a backplane or cross-board (backplane systems), especially if “hot-swap” nodes are required. As a rule, uniform signal levels are adopted on the backplane, and the task of peripheral board developers is to choose the right interface means. It should be noted that over a long history, TTL levels have become the de facto standard for backplanes and in-house (or in-house) interfaces. Therefore, with the development of existing systems and the use of a new element base, it becomes necessary to interface new boards with a common bus. For these purposes, there is a whole range of solutions.

As you know, classic TTL and CMOS IC families provide a load current of up to 24 mA with a minimum line impedance of 50 ohms. With the advent of BiCMOS technology, it has become possible to achieve an output current of -32/64 mA and drive a line with an impedance of 25 ohms. For these purposes, the SN74ABT25xxx IC family is adapted. These microcircuits can also be used in systems of so-called "hot-swapping" of modules, removable modules can be connected or disconnected during operation of the device.

When designing plug-in modules, several requirements must be met, which, firstly, will prevent the module from breaking when connected to a running system and, secondly, will not lead to system failures. Let's consider them.

The interface between the plug-in and main modules consists of power, ground, and signal buses. The model of the microcircuit connected to the system is shown in fig. 6.

Rice. 6. Diodes at the input and output of the IC

Protection of inputs and outputs of microcircuits is carried out using diode switches.

Diodes D3 and D4 are used to protect the outputs. Diode D3 is used in CMOS chips for ESD protection. Diode D4 protects against output voltage less than logic zero.

When designing plug-in modules, it is better to use BiCMOS chips, because they compare favorably with others in that they have a circuit (Fig. 7) that keeps the chip output in a high impedance state at the moment the chip is turned on. This circuit monitors the supply voltage and consists of two diodes D1 and D2 and a transistor Q1, the base of which is energized. When the supply voltage is less than the set one (for example, for ABT / BCT series VCOFF ~ 2.5 V, for LVT VCOFF ~ 1.8 V), the output of this circuit goes into a logic one state. At the same time, it turns off the signal at the output of the microcircuit, regardless of the input. This property of BiCMOS chips ensures that the behavior of the circuit is predictable even at very low supply voltages.

Rice. 7. A circuit that turns off the output at low supply voltage in BiCMOS microcircuits

When a module is hot-plugged, system behavior will be predictable if at least two conditions are met:

• the connector has one or more ground pins pushed forward relative to the other pins;
• The interface consists only of bipolar or BiCMOS ICs with tri-state or open-collector outputs.

The problem of bus collisions is especially acute when output signals are encountered. different levels- low and high. On fig. 8 shows this process. The current that occurs as a result of the conflict reaches 120 mA, and in this struggle, the microcircuit that has a low output level survives. A high-output IC operates in short-circuit mode and burns out.

Rice. 8. Short-circuit current during bus conflicts

To avoid this conflict, additional circuitry is needed to keep the outputs in a high impedance state during power-up.

The main element of this circuit can be the TLC7705 IC. Such microcircuits are used to generate a RESET signal when the device is turned on. In our case, the outputs of this microcircuit are connected to the enable inputs of the bus drivers. During the initialization or switching on of the module, the RESET signal switches the outputs of the microcircuits to the third state. When creating such circuits, it is convenient to use microcircuits that have two ENABLE inputs (for example, SN74ABT541). This solution is shown in Fig. 9.

Rice. 9. Monitoring bus conflicts

There are bus shapers that already contain all the components necessary to protect against bus conflicts - switches and resistors. These chips are available in two series: ETL (Enhanced Transceiver Logic, SN74ABTE series) and BTL (Backplane Transceiver Logic, SN74FB series).

The ETL-series ICs have an additional pin for connecting the charging voltage of the IC's output capacitance, commonly referred to as VCCBIAS. It powers the circuit that charges the capacitor when the module is turned on.

On fig. 10 shows an interface diagram using an ETL chip. At the moment the module is turned on, after connecting the VCC1 and GND contacts, the VCCBIAS voltage appears on the U3 chip. At the same time, the U2 and U1 microcircuits are turned on and, with the OE signal, the outputs of the bus driver are disconnected from the bus.

Rice. 10. Interface diagram using ETL series chips

Voltage surges in the power circuits of the system when the module is connected appear in the same way as surges in the signal circuits. In this case, the value of the capacitance being charged varies from tens to hundreds of microfarads and depends on the capacitance of the blocking capacitors on the connected board. One way to limit the power surge is to include a switch in the power circuit that turns on slowly. On fig. 11, a circuit is proposed in which the P-MOS transistor plays the role of a switch. The RC circuit provides a slow signal change at the base of the transistor. Diode D quickly discharges the capacitor after the module has been turned off.

Rice. 11. Scheme of slow turning on the module using a transistor

It is assumed that the transistor has a low resistance in the on state. During operation, the power dissipated in the transistor is small due to the small voltage drop. If necessary, several transistors can be connected in parallel.

Plug-in modules conveniently use their own power supplies.

On fig. Figure 12 shows a power supply circuit that receives from ten to forty volts from the system and converts them in a pulsed manner to 5 V. The circuit does not give a voltage surge when turned on.

Rice. 12. Decentralized power supply

Literature

1. Steshenko VB School of circuit design of signal processing devices. // Components and technologies, No. , , 2000
2. Steshenko V. School for the development of digital signal processing equipment for FPGAs Chip News, 1999, No. 8–10, 2000, No. 1, 3–5.
3. Steshenko V. ALTERA FPGA: design of signal processing devices. M.: Dodeka, 2000.
4. Alicke F., Bartholdy F., Blozis S., Dehemelt F., Forstner P., Holland N., Huchzermier J. Comparing Bus Solutions, Application Report, Texas Instruments, SLLA067, March 2000.
5. Steshenko V. ACCEL EDA: design technology printed circuit boards. M.: "Knowledge", 2000, 512 p., ill.

INTERFACE is a standardized environment turn a way to exchange information between two or more pieces of equipment: instruments, controllers, personal computer, etc.

Interfaces for information exchange between devices used in industry can be of two types:

"point-to-point", connecting two devices to each other;

multi-device, allowing you to connect more than two devices to one data line.

The main characteristic of the interface is the bandwidth, which shows how many bits of information are transmitted over the interface in 1 second and is measured in bits per second (bps, Mbps), or bits per second (bps, Mbps). Please note that this bandwidth includes the "overhead" associated with the method of data transmission. For different interfaces and protocols, the share of useful information transmitted per second can be from 30% to 90% of the total throughput.

A PROTOCOL is a standardized set of rules for transmitting information over an interface.

For complex protocols, it is common practice to divide them into several levels (layers). In this case, each level is implemented separately and the exchange between the levels is additionally standardized. It also allows you to replace some layers (for example, to adapt to different interfaces), while leaving others unchanged.

Interfaces and protocols used in instruments and controllers

Instrument Compatibility is their ability to carry out information exchange among themselves. Each of the devices participating in the information exchange must have a specific interface and understand a specific protocol. And even in this case, the possibility of an exchange is not guaranteed, because. one device may not be able to transmit the information that another needs to receive. But what if the devices are capable of transmitting the necessary information, but have different interfaces and / or understand different protocols? In this case, the use of interface converters or gateways is required.

Interface converter- a device that has two or more different interfaces, relaying information from one interface to another (others). In this case, the transmission of information is carried out without its transformation. Therefore, it makes sense to connect to the interface converter only those devices that are capable of operating using the same protocol.

Gateway(or bridge) is an intelligent device capable of converting data from one protocol to another. In this case, the gateway can also act as an interface converter. The gateway, unlike the interface converter, requires additional configuration, because it needs to specify which data should be received and transmitted using which protocols.

InterfaceRS-485. When designing industrial automation systems, information networks based on the interface of the EIA RS-485 standard are most widely used. This is a high-speed and noise-resistant serial interface that allows you to create networks by connecting many devices in parallel on one physical line.

Most devices designed to work in an information network have a built-in RS-485 interface.

In an ordinary personal computer (not an industrial version), this interface is not available, therefore, to connect an industrial RS-485 network to a PC, a special adapter is required - an RS-485 / RS-232 or RS-485 / USB interface converter (for example, OWEN ASZ-M or AC4).

Data is transmitted via the RS-485 interface using a "symmetrical" (differential) signal over two lines (A and B). The maximum length of the communication line between the end devices can be up to 1200 m (or more using repeaters). With a communication line length of more than 100 m, it is recommended to install terminating resistors with a nominal value of 100 to 250 ohms at the most distant points of the network from each other, which allow compensating the wave impedance of the cable and minimizing the amplitude of the reflected signal. The number of devices in the network must not exceed 32 (without the use of a repeater).

InterfaceRS-232. The EIA RS-232C interface is designed for serial communication of two devices (point-to-point connection). It is common and widely used for connecting external equipment to a PC. Data transmission via the RS-232C interface is carried out using an "asymmetric" signal along two lines - TxD and RxD, and the signal amplitude is measured relative to the GND ("zero") line (see Fig.).

The asymmetry of the signal causes low noise immunity of this interface, especially with industrial interference, so the length of the RS-232 communication line is usually limited to a distance of several meters. The presence of lines for receiving (RxD) and transmitting (TxD) data allows you to support full-duplex transmission of information, i.e. information can be both transmitted and received at the same time. Devices for RS-232 communication are usually connected by a cable with 9-pin or 25-pin connectors (DB9, DB25, etc.).

Current loop interface(variant of RS-232). "Current loop" - a kind of RS-232 interface, which also provides communication between two devices (point-to-point connection). Information in the current loop is transmitted not by voltage, but by current through a two-wire line, which provides a high level of noise immunity. The "current loop" standard allows data to be transmitted over distances up to 1000 m at speeds up to 19.2 kbps. Due to the presence of one communication line, the standard provides half-duplex data transmission, i.e. At any moment in time, information can either be transmitted or received.

Instruments may have a built-in current loop interface that can be connected to:

1) to a PC via a current loop/RS-232 adapter;

2) to the RS-485 network through the current loop/RS-485 gateway.

Rice. Typical schemes for connecting devices with an interface

"current loop" to the network

Interfaceethernet. Ethernet is a transport technology for data transmission in computer networks, mainly local ones. The protocol used in Ethernet cable networks is CSMA/CD (Carrier Sense Multiple Access with Collision Detection) - Carrier Sense Multiple Access with Collision Detection. In accordance with this protocol, devices begin data transmission only after detecting a free communication channel in order to reduce the number of collisions (errors) between them. All versions of the Ethernet family are designed to support up to 1024 network nodes. This interface has become widespread in computer networks due to its high bandwidth and noise immunity. The built-in 10/100 Base-T Ethernet interface is more commonly used, which allows devices and PLCs to be integrated into higher-level distributed information systems.

InterfaceUSB. The USB standard was developed as an alternative to the slower RS-232 and LPT computer standards. USB 2.0 devices currently allow data transfer rates up to 480 Mbps.

The USB interface, like RS-48S, is symmetrical and allows you to transfer data over two wires (D+ and D-), while the logical levels are similar to the corresponding levels of the RS-485 standard. The USB interface has Vcc and GND power lines to power the connected device (provided that the current drawn by it does not exceed 500 mA). After installing the driver, the operating system recognizes the connected device as a COM port and uses the standard asynchronous data transfer mode used to work with a hardware COM port.

Data interfaces are evolving so fast that it's hard for storage manufacturers to keep up with them. Every year, interfaces appear that allow you to achieve data transfer rates many times greater than existing devices. Switches and network adapters start supporting the latest high-speed interfaces long before they become available in storage systems.

The table below shows the evolution of throughputs of storage connectivity interfaces over time.

Interface trends

Estimated years of new data rates for various interfaces based on industry research are described below. History shows that for many interfaces, the development cycle of new standards is 3-4 years.

It should be noted that from the moment the specification of a new interface is approved and until the appearance on the market of products that support it, it usually takes several months. The widespread adoption of the new standard may take several years.

Also, work is underway to develop versions of existing interfaces with reduced power consumption.

fiber channel

32Gbps FC (32GFC)

Work on the 32GFC standard, FC-PI-6, began in early 2010. In December 2013, the Fiber Channel Industry Association (FCIA) announced the completion of the specification. Products supporting this interface are expected to hit the market in 2015 or 2016. 32GFC will use 25/28G SFP+ connector.

The FC 128Gb multi-channel interface, known as 128FCp (parallel quad), is based on FC 32Gb technology and added to the official roadmap for the FC standard. The T11 committee named the project FC-PI-6P. Completion of the specification is planned for late 2014 - early 2015, products will become available in 2015 or 2016. 128GFCp will probably use QSFP+ connectors, and support for CFP2 or CFP4 connectors is also possible.

Some vendors refer to 32GFC and 128GFC as "Gen 6" Fiber Channel since this version supports 2 different data rates in 2 different configurations (serial and parallel).

64Gbps FC (64GFC), 256Gbps FC (256GFC)

Development of the 64GFC and 256GFC standards began in the FC-PI-7 project. Technical stability is expected in 2017. Each revision of FC is backward compatible with at least two previous generations.

FC as SAN interface

Apparently, Fiber Channel will remain the main technology for building SANs for the foreseeable future. Significant investments (billions of US dollars) have been invested in FC infrastructure over the years, mainly in data centers that will function for many more years.

FC as disk interface

Fiber Channel as a drive interface is becoming a thing of the past as enterprise-class drive vendors move to 6Gbps SAS and 12Gbps SAS. Due to the relatively high volume of 3.5-inch FC drives used in enterprise disk subsystems, it is expected that FC will be used for some time to support them. Among 2.5-inch drives, the Fiber Channel interface is likely to be available on a very small number of devices.

Fiber Channel over Ethernet

FCoE (FC-BB-6)

Work on the FC-BB-6 standard was completed by T11 in August 2014. FC-BB-6 standardizes the VN2VB architecture and improves Domain_ID scalability.

VN2VN is a way to directly connect FCoE (Virtual N_Ports) end nodes without the need for FC or FCoE switches (FC Forwarders), allowing for simplified configuration in small deployments. This idea is sometimes referred to as "Ethernet Only" FCoE. These networks do not require zoning, resulting in less complexity and lower costs.

Domain_ID Scalability (Domain_ID Scalability) allows FCoE fabrics to scale to larger SANs.

40Gbps and 100Gbps

40Gbps FCoE is a year or two away. Perhaps the interface will appear simultaneously with 32Gb FC. The IEEE 802.3ba 40Gbps and 100Gbps Ethernet standards were ratified in June 2010. New products should be available over time.

It is likely that 40Gbps and 100Gbps FCoE based on the 2010 Ethernet standards will be used initially for ISL cores, leaving 10Gb FCoE mostly for end connections. Future versions of 100GFCoE cables and connectors are expected to be available in 10x10 and then 4x25 configurations.

InfiniBand

Currently, products using 100Gbps Infiniband EDR (Enhanced Data Rate) are already commercially available. EDR uses 25/28G SFP+ connectors, as well as Ethernet and Fiber Channel interfaces.

InfiniBand High Data Rate (HDR), supporting 2x the speed of EDR, is expected in 2017 or 2018. HDR host adapters may require PCIe 4.0 slots.

ethernet

In July 2014, 2 different industry groups - 20G/50G Ethernet Consortium and IEEE 802.3 25Gb/s Ethernet Study Group - announced new work on the Ethernet specification to take advantage of 25Gb PHY in single lane configuration. The result was a single-band connection specification similar to existing 10GbE technology, but 2.5 times faster. Products using these technologies are already available. It is also planned to develop a 50GbE standard using 2 25GbE lanes. The completion of the specification is planned for 2018-2020.

2.5GbE and 5GbE standards are under development, which allow for cost-effective increases in network bandwidth using Category 5e cabling. The NBASE-T Alliance released version 1.1 of the NBASE-T specification, which describes the physical layer implementation. The Technical Working Group is working on the specification for the PHY-MAC system interface, magnetic and channel characteristics. In addition, employees of 25 companies participate in the development of IEEE 802.3bz 2.5/5GBASE-T standards. Products supporting 2.5GbE and 5GbE are already appearing on the market.

SAS

12Gbps SAS

The SAS 3 specification, which includes 12Gbps SAS, was submitted to INCITS in Q4 2013. 12Gbps SAS products for end users began to appear in the second half of 2013, including SSDs, network adapters (SAS HBAs), and RAID controllers. 12Gbps SAS allows you to take full advantage of the PCIe 3.0 bus.

24Gbps SAS

The 24Gbps SAS interface specification is currently under development. It is predicted that the first components using 24Gbps SAS may appear in 2016 or 2017, the first products for users will be available in 2018. 24Gbps SAS is designed to be fully compatible with 12Gbps and 6Gbps SAS. Perhaps a different coding scheme will be used.

Prototypes of the 24Gbps SAS interface will use PCIe 3.x technology, however it is likely that final products will use PCIe 4.x technology.

SCSI Express

SCSI Express implements the well-known SCSI protocol over the PCI Express interface, reducing latency through the use of PCIe. It is being developed to match the improved speed of SSD drives. SCSI Express uses the SCSI over PCIe (SOP) and PCIe Queueing Interface (PQI) protocols, creating the SOP-PQI protocol. Controllers connect to devices using the SFF-8639 connector, which supports multiple protocols and interfaces such as PCIe, SAS, and SATA. SCSI Express supports PCIe devices using up to 4 lanes.

SCSI Express was first proposed in 2011 and accepted as a formal project in 2012, but was not developed until 2015. It is not yet known when the first SCSI Express products will be released to the market.

SAS Connectivity

New SAS connectivity options allow data to be transferred over long distances using active copper patch cords and fiber optic cables. The Mini SAS HD connector (SFF-8644) can be used for 6Gbps SAS and 12Gbps SAS.

In the future, features such as support for the Zoned Block Commands (ZBC) command set and Shingled Magnetic Recording (SMR) recording technology for larger discs are expected.

SATA Express

The SATA Express specification is included in SATA Revision 3.2. SATA Express allows client SATA and PCIe solutions to coexist. SATA Express enables transfer rates up to 2 PCIe lanes (2GBps for PCIe 3.0 and 1GBps for PCIe 2.0) over the current SATA technology (0.6GBps). This speed is suitable for SSDs and SSHDs, while ordinary HDDs can continue to use the existing SATA interface. Each device can use a PCIe or SATA connector, but not both at the same time. A separate signal generated by the device tells the host whether the device is SATA or PCI Express. As of mid-2015, SATA Express is supported by a very small number of motherboards. While it is not clear whether SATA Express will be accepted by the market, we should not expect a large number of products in the near future.

New SATA Features

New features planned for the future include enterprise-level options such as remote power off, improved array recovery, and optimizations for NAND flash devices. Support for SMR (Shingled Magnetic Recording) technology is also planned.

Thunderbolt

Thunderbolt 2 was introduced at the end of 2013, many devices are now being released using given interface. Thunderbolt 2 transfer rate is 20 Gbps.

Thunderbolt 3 (40 Gbps) was announced in June 2015. Uses a USB type-C cable that supports USB 3.1 (10 Gbps), Display Port (dual 4k displays), 4 PCI Express 3.0 lanes, and previous versions of Thunderbolt. In addition, it provides 15 watts to power connected devices and supports USB power to charge laptops up to 100 watts. Active copper and fiber optic cables support data rates up to 40 Gbps. Less expensive passive copper cables support speeds up to 20 Gbps. The first products using Thunderbolt 3 are expected to appear in late 2015. Many more devices will become available in 2016.

USB

USB 3.1

In July 2013, the USB 3.0 Promoter Group announced the creation of the USB 3.1 specification. The new interface allows operation at 10 Gbps and is fully compatible with previous versions of USB. USB 3.1 uses a 128b/132b encoding scheme in which 4 bits are used for protocol control and cable information. Devices using USB 3.1 with the new Type-C cable are already on the market.

USB power

USB is an interface with the ability to power connected devices, and more and more devices are being charged or powered by USB. The USB Power Delivery (PD) specification version 1.0 was released in July 2012. It was proposed to increase the power supply from 7.5 watts to 100 watts, depending on the type of cable and connector. Devices must negotiate with each other to determine the voltage and current to transmit electricity, and it is possible to transfer energy in any direction. Devices can adjust the power supply during the transmission of information. Prototypes of USB PD devices began to appear in late 2013. The USB PD specification is included in the USB 3.1 specification.

USB Type-C cable

The specification for the new cable and connector was finalized in August 2014. This cable has a significantly different design with a reduced connector size that can be easily applied to a variety of devices. According to the new specification, the cable and connector can be used in any position, regardless of the orientation of the connector and the direction of the cable. The cable has the same type of connector on both sides. The first Type-C USB cables are passive copper cables up to 1m in length, active copper and fiber optic cables are expected soon.

The growing volume of implementation of a wide variety of automation systems in all areas of industry requires the processing of an ever-increasing amount of information. The “main arteries” are serial data cables that control complex processes and transmit process measurements.

Various types of serial interfaces are widely used, which guarantee noise-free high-speed data transmission in harsh industrial environments.

RS-232 (V.24)

One of the most common serial interfaces is defined in the TIA-232 and CCITT V.24 standards.

The interface implements data exchange between two devices (point-to-point connection) in duplex mode at a distance of up to 15 m.

The simplest configuration requires three wires - TxD (transmit data), RxD (receive data) and GND (signal ground). In this case, the control of data transfer is carried out with the so-called software acknowledgment. For software handshake transmission, there are additional lines used for transmission of control signals, clock signals, and also for signaling.

Device interfaces can be designed as Data Communication Equipment (DCE) or Data Processing Equipment (DTE). A distinguishing feature is the different direction of transmission on the lines with the same designation and pin assignment. Example: A DTE device transmits over a TxD (transmit data) connection, while a DCE device receives data over the same connection. This solution allows for simple direct communication between two devices. When connecting devices of the same type, all connecting lines must be crossed.

The signal levels of both data lines are defined as follows:

• -3 to -15 for boolean "I"
• +3 to +15 for boolean "0"

On the transmission lines of control and notification signals, the logic of operation, on the contrary, is inverted (log. "I" = positive potential). The maximum data rate is 115.2 kbps. In industrial conditions, the transmission distance in this case is recommended to be reduced to 5 m.

TTY

The current loop TTY interface was first used in telegraphy. Nowadays it can still be found in (PLC) and printers. Both transmitting and receiving data require one pair of lines, and the lines must be twisted in pairs. Data transmission is carried out in duplex mode with software handshaking. Control signal transmission lines are not provided. The current value of 20 mA in the loop corresponds to the logical "I" state. If the current circuit is broken, this is perceived as a logical "0" state. Each loop requires a current-generating source, which can be connected either on the transmitting or receiving side. The side that generates the current is considered "active", while the "passive" is always opposite the active. There are three interface configurations:

1. Fully active TTY interfaces with current sources in both transmitter and receiver legs.
2. Passive TTY interfaces without corresponding constant current sources.
3. Semi-active TTY interfaces with power supply on the transmit side (TD) only.

The receiver (RD) is passive. Each current loop can operate with only one current source. Only "fully active/passive" and "semi-active/semi-active" combinations are allowed. Such data transmission can be realized over distances up to 1000 m. The maximum transmission rate is 19200 bps.

RS-422

The requirements of intelligent machines for fast and high-performance data communication are described by the RS-422 standard. Serial data transmission between two devices is carried out in duplex mode at speeds up to 10 Mbps over distances up to 1200 m.

The electrical levels in data lines are defined as follows:

• -0.3 to -6 for logical "I"
• +0.3 to +6 for logical "0".

The signal state is characterized by the voltage difference between the measuring points (A) and (B). If the voltage at point (A) compared to the voltage at point (B): - Negative, then the data line is a log. I, control line - log.0, (UA-UB-0.3 B).

Terminated load resistances (100…200 ohms) at the receiver inputs not only prevent reflections in the transmission line, but also further increase transmission reliability due to a clearly defined resultant current.

RS-485 W2

This type of serial interface not only has the same high performance as the RS-422 interface, but also allows multidrop connection of up to 32 end devices. The electrical levels and their associated logical values ​​are identical to those defined by the RS-422 standard. however, due to the 2-wire connection, data transmission can only be carried out in half-duplex mode, which means that data transmission and reception are performed alternately and must be controlled by the appropriate program. The corresponding software protocol must, in contrast to pure point-to-point communication, provide the ability to address each terminal device connected in a multipoint scheme by address, as well as identify this device. Only one end device can transmit data at a time, all the others must be in the "listening" mode at this time. A two-wire bus cable can have a length of up to 1200 m, and terminating load resistors (100 ... 200 Ohm) must be connected at both ends. Individual terminations can be separated from the bus by up to 5 m using spurs. With twisted-pair and shielded cable, the maximum data transfer rate is 10 Mbit/s. The RS-485 standard defines only the physical properties of the interface. Therefore, the compatibility of RS-485 interfaces with each other is not necessarily guaranteed. Parameters such as baud rate, data format and encoding are determined by system standards, such as INTERBUS, PROFIBUS, MODBUS, etc.

RS-485 W4

The 4-wire RS-485 standard allows, in contrast to the 2-wire RS-485 standard, full-duplex bus communication. An example of this is the DIN-Messbus measuring bus. In contrast to 2-wire technology, in this case the receiver's transmission branches are separated from each other and can therefore operate simultaneously. Topologies based on the master/slave principle are preferably used in measuring bus systems, in which the master transmits data to up to 32 listening slaves. Transmission branches of slave devices can be in the third discrete state (tri-state), in which their high impedance is maintained. Only the measuring station that has received the request actively connects its transmitter to the bus. The electrical levels and their logical values ​​correspond, as in all other RS-485 type interfaces, to the RS-422 standard. The maximum transfer rate is 10 Mbps. The bus cable must be terminated, its cores must be twisted in pairs and shielded.

Modem

The conventional telephone network only allows the transmission of analog signals in the frequency range from 300 Hz to 3.4 kHz. Therefore, in order to transmit digital signals from serial interfaces through the telephone network, preliminary conversion is necessary. This requires a device that converts the digital data stream into analog waveforms, and these waveforms then back into a digital data stream. These processes are called modulation and demodulation, and the device that performs them, respectively, is a modem. The process of formation of dial-up communication complies with international standards. In this case, the carrier frequency serves to synchronize both modems. Using the public telephone network, you can thus implement a channel between devices located anywhere in the world. But even when using a leased line, distances of 20 km are not a problem.

Although only two wires are required, data transmission most often occurs in duplex mode.

The maximum analog line throughput is 33.6 kbps.

V.90 transmission at 56 kbps is only possible from the Internet server to the modem. In the opposite direction, i.e. from V.90 modem to V.90 modem, the transfer rate is 33.6 kbps maximum.

INTERBUS

INTERBUS is a ring system. Transmitting and receiving lines are combined into one cable, because of this, INTERBUS is perceived as a tree structure with lines represented by branches from the main cable. These spurs are connected to the remote bus via bus spur terminals. Connections between remote bus terminations are active point-to-point connections, the physical layer conforms to the RS-422 standard. In this case, useful data is transmitted as differential signals over twisted pairs of dual wires (4 wires) in full duplex mode. The data rate is 500 kbps or 2 Mbps. The possible total length of communication lines is up to 12.8 km, while the system can include a maximum of 255 segments up to 400 m each.

The use of repeaters and terminating resistors at the end of the line is not required because the ring is automatically closed at the last device on the remote bus.

PROFIBUS

The PROFIBUS bus is defined by the IEC 61158 and IEC 61784 standards and is technically based on a 2-wire RS-485 system with half-duplex communication. The Profibus system is built as a purely linear structure with the possibility of connecting up to 32 devices, with a maximum bus segment length of 1200 m. for Profibus. The end devices of the Profibus system are interconnected by laying a two-core bus cable with twisted cores. If more end devices are to be networked, the machine or industrial plant must be segmented. Separate segments exchange data with each other through repeaters, which provide amplification and separation of signal potentials that carry useful information. Each repeater expands the system by one additional segment with 32 terminations and a total cable length for a maximum of 127 terminations. The baud rate in Profibus systems can be configured from 9.6 kbps to 12 Mbps. The speed value affects the allowed length of bus segments as well as passive taps (table). To ensure reliable data transmission, each Profibus bus segment on a copper cable must start and end with a terminating resistor.

CANopen/Device Net

Protocol local network controllers (Controller Area Network (CAN)) was originally developed for networking automotive electronics. By extending the protocol, CANopen and Device Net systems have been obtained for industrial fieldbus applications.

All bus terminals are connected linearly with a three-core cable having terminating resistances at the beginning and at the end.

End devices listen for data exchange on the bus and, after waiting for a pause, start transmitting data packets. Often several end devices will identify the bus as free and start data transfer at the same time. Since different data packets could interfere with each other, bit-by-bit arbitration is provided to prevent data loss. This mechanism is called Carrier Sense Multiple Access with Collision Avoidment (abbreviated as CSMA/CA - Carrier Sense Multiple Access with Collision Avoidance).

The end devices compare the signal levels on the bus with the signal levels they are transmitting. These levels can be either dominant (level 0) or recessive (level I). As soon as a dominant level is written over its own bit pattern, this means that the other terminal device has switched to transmit mode. A transmitter that turns out to be recessive immediately stops its transmission and will try to transmit its data packet again during the next pause. Messages, and thus requests for access to the bus, can be prioritized when assigning addresses depending on the number of dominant bits.

The signal propagation time limits the maximum achievable network length depending on the transmission rate, since the CSMA / CA method works only in a limited time window. This must be taken into account when designing.

ethernet

Ethernet is described in the IEE 802 standard and was originally designed for communication between office devices (computers, printers, etc.). In this case, a linear topology was adopted and a coaxial cable was used. Currently, networks are built exclusively with a decentralized star topology based on twisted pairs or fiber optic cable. At the same time, in industrial networks, the data transfer rate is 10 or 100 Mbps. The network structure can be adapted to the requirements of each individual case by organizing cascades using star splitters (hubs, switches, routers).

If hubs are used for data distribution, the system must operate in half-duplex mode. In this case, data exchange is provided by the Carrier Sense Multiple Access with Collision Avoidment (CSMA/CA - Carrier Sense Multiple Access with Collision Avoidance) mechanism. In this case, the terminal devices listen to the information exchange channel in the network and start data transmission only after the suspension of other transmissions. The packet is sent to each end device on the network. End devices compare the destination address contained in the sent packet with their own address and accept the packet only if the addresses match. Often several end devices will identify the bus as free and start data transfer at the same time. As a result, data packets destroy each other. In this case, one speaks of a collision. The active end device that first detects a collision promptly requires all end devices to slow down the data transfer. To ensure that data packets are not lost and can be sent again, transmitters must receive an acknowledgment message before the last bit of the message has been sent.

The time constraints of the acknowledgment message in a collision directly affect the maximum network length. The so-called collision domain is limited to a network adapter, router or switch. This segmentation of the network eliminates the limitations of a network with concentrators, which makes possible a large territorial extent of the network and optimization of data exchange.

Ideally, each end device is connected to a switching port, thereby obtaining its own collision domain. Network performance is improved because collisions are eliminated, the CSMA/CD mechanism can be disabled and the network can be operated in full duplex mode in double-width bandwidth.

During installation, the type of device used must be taken into account. According to the DTE/DCE interfaces, in the case of RS-232 devices, there are Ethernet devices with MDI or MDIx interfaces. Devices of the same type must always be connected with connecting cables with crossed wiring, and devices of different types with cables with 1:1 wiring.

With internal switching that combines multiple devices, it is possible to switch the interface manually or automatically (auto-negotiation function) directly at the installation site. As a result, in all cases it is possible to connect with a cable with a 1:1 wiring.

Another automatic mechanism is the auto-negotiation of speed and mode of operation, thanks to which devices select a common speed and transmission mode (half duplex or full duplex) for all.